Method and apparatus for scalable and super-scalable information processing using binary gate circuits structured by code-selected pass transistors

ABSTRACT

A processing space comprises an array of transistors empowered by forming connections through circuit pass transistors to power and data input/output means and connections therebetween through signal pass transistors. By structuring the needed circuits at the site(s) of the data the von Neumann bottleneck is eliminated, which increases the computing power of the apparatus substantially, thus to enable non-stop Information Processing on steady streams of data and code, with no repetitive instruction and data transfers required. That code will identify the physical locations of every transistor in the processing space, and will enable only the pass transistors therein needed to structure the circuits of any arithmetical/logical algorithm in a processing space of any size, speed, and level of computer power. By joining one processing space to another the apparatus also exhibits super-scalability.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Application is a Divisional Application of U.S. patent application Ser. No. 11/542,773, filed Oct. 2, 2006, which application is relied upon for priority and by this reference is deemed incorporated herein as though fully set forth herein. Applicant is the sole inventor of the invention that is the subject of the above-cited patent application and of the present invention, and has resided in Lincoln City, Oreg., USA, throughout the creation and filing of the present patent application and the above-cited patent application.

RESERVATION OF COPYRIGHT

This patent document contains text and images that are subject to copyright protection. The copyright owner, who is the present inventor and author of this patent application, has no objection to facsimile, electronic, or other means by which anyone might copy the patent document herein or the patent, or parts thereof, as these appear in the U.S. Patent and Trademark Office files or records, or to copying in accordance with any contractual agreements executed by that owner, but otherwise reserves all domestic and foreign copyright rights whatsoever, all of which rights are fully reserved.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable

REFERENCE TO A “SEQUENCE LISTING”

Not applicable

BACKGROUND OF THE INVENTION

It has often been the case in both science and engineering that solutions to long-known problems are found at the most primitive level of the subject matter. Such was the case here. This patent application relates to “Information Processing” (IP) in general, and specifically to methods and apparatus that carry out that IP by the use of procedures that eliminate the “von Neumann Bottleneck” (vNB). The circuits required for each step of an algorithm are electronically structured within a “Processing Space” (PS) in advance of the entry or formation of the data that are to be operated upon, and after such usage those circuits are de-structured for other uses of the elements involved. As a result, the vNB is removed, and a continuous, uninterrupted flow of IP is brought about.

A principle characteristic of the apparatus is its fine-grained nature, wherein the operational components of that PS (such as single operational transistors) are to be interconnected through Pass Transistors (PTs) both within the bounds of a particular PS and along the peripheries thereof when two or more PSs are joined together. The former process exhibits scalability, while super-scalability is brought out through the latter process.

The above-cited U.S. patent application Ser. No. 11/542,773, filed Oct. 2, 2006, and fully incorporated herein by this reference, traces out a short history of the development of computers, and further contains the results of searching both the patent and the technical literature, from which no document or other evidence of the basic “IL” procedure set out herein having been practiced, or even suggested or contemplated, could be found.

The course of computer development had been set until now by Babbage in his adoption of the only procedure that was available to him with a mechanical computer. In seeking to convert such a single-function kind of device into a general purpose computer, it was natural enough simply to expand upon that Babbage concept, i.e., to provide a number of different calculating capabilities within the device, and then add instructions by which the user could select which functions were to be used in each step. Even had just a single instruction been needed at the outset, that would select just some one process to be carried out, with that development path having been started, the need for both data and instruction transfers was initiated. A part of the operations carried out by the device would then no longer be devoted entirely to the making of binary logic decisions (or decimal calculations, if that were the case), but instead to the task of transmitting data and (possibly) instructions back and forth between the operating circuits and memory.

With larger and more complex algorithms later to be developed, there would be particular operational sequences that would be the same for any number of different algorithms, and in any event it would not have been possible to provide a single complex circuit that would carry out those more complex operations from beginning to end, so the desired circuit sequences came to be broken up into smaller segments. That ultimately led to the operational functions and instruction sets of microprocessors. That economy in terms of hardware needs, however, necessitated the production of intermediate results that would then have to be saved in memory and brought back later for use when required. The need to transfer data and instructions was then multiplied by the number of different segments into which what would by that time have come to be called a program would now be devoted to matching instruction with the data, thus to increase even further the amount of computer time devoted to operations other than making arithmetic/logical decisions. The limits to which that process can be expanded are now coming to be recognized.

To begin this development, in 1822 Charles Babbage had conceived his “Difference Engine,” and then in 1834 his “Analytical Engine,” in which “ . . . numbers would be brought from the store to the arithmetic mill for processing, and the results of the computation would be returned to the store.” M. Campbell-Kelly and W. Aspray, Computer: A History of the Information Machine. New York: Basic Books, 1996, p. 55. In the Difference Engine, those data had to be entered manually, but then with the cranking of a wheel the calculations would proceed. One of Babbage's goals, an automatic calculator, had thus, to an extent, been achieved.

A “limited” general purpose computer was then achieved in the Analytical Engine (on paper only since unfortunately, Babbage had not ever got one fully built), for which the basic process thereof is seen in the “A” entry of FIG. 1 (sheet 1). As to that apparatus, Doron Swade, Charles Babbage and the Quest to Build the First Computer: The Difference Engine (Penguin Books, New York, 2002), pp. 105-16), says the following:

-   -   It is a startling fact that the logical and physical separation         of the Store and Mill (memory and central processor) is a         fundamental feature of the modern electronic digital         computer. * * * This layout, which became known as ‘von Neumann         architecture’, has dominated computer design to the present day,         and is incorporated in just about every computer around. A         feature of this article is the separation of the central         processor from the memory—a feature explicitly used by Babbage         over a century earlier.

Then in 1950, Alan M. Turing gave an example of an instruction as “add the number stored in position 6809 to that in 4302 and put the result back into the latter storage position” A. M. Turing, “Computing Machinery and Intelligence,” MIND, Vol. 59 (October, 1950), pp. 433-460. In preparing his PhD thesis, the present inventor followed the “Op Code-Address A-Address B-Address C” method described by M. W. Wrubel in A Primer of Programming for Digital Computers (McGraw-Hill Book Co., Inc., New York, 1959), pp. 22-23, using the famous “IBM cards” by which the Princeton University IBM 650 executed programs. The procedure described by Turing and that set out by Wrubel differed only in that the destination address referred to by Turing was the same as that to which the result of the procedure was stored, while for Wrubel (and the present author), using that same procedure the “C” address was different. The basic processes of this “von Neumann computer” are shown in the “B” entry of FIG. 1.

In that “A” entry in FIG. 1, the dark circles represent the process of moving numbers from the “store” to the “mill” for processing, with the results then being returned to the “store,” as shown by the arrows. In the analogous representation of current practice in the “B” entry of FIG. 1, that same principle can be seen to be in operation. Current computers constitute the general purpose device that Babbage had sought, and with storable programs perform a variety of tasks such as Babbage could scarcely have imagined, but at the cost of exacerbating the vNb problem in that the achievement of “general purpose” operation required instructions to be transferred to the CPU as well as data.

The oppositely-directed circular arrows between the “Data In” and “Store” boxes in the “Babbage Paradigm” and between the “Data In” and “Memory” boxes of the “von Neumann Paradigm” both constitute that vNb. If one were to construct a super-computer using 10,000 or more microprocessors in which that same architecture is exhibited, such as in a “Massively Parallel Processing” (MPP) design, G. J. Lipovski and M. Malek, Parallel Computing: Theory and Comparisons (John Wiley & Sons, New York, 1987), p. 10, one would then have installed 10,000 or more vNbs, and the time required for all those data and instruction transfers to be carried out would then be wasted 10,000 or more times over. (There would have been a “traffic jam,” of course, but this was ultimately at least ameliorated by providing different busses for the data and for instructions. Even so, one problem was still to be faced, in which different programs or parts of a single program would want access to the same memory address at the same time.)

Developments along that electronic Babbage path to the current processes of entry B in FIG. 1, particularly those of parallel processing, Field Programmable Gate Arrays (FPGAs), and the like, can ultimately be traced broadly through the Fleming vacuum tube in 1904, the de Forest triode in 1906, Konrad Zuse's use of binary logic and Boolean algebra in the late 1930's and '40's, and Eckert and Mauchly's ENIAC that first employed vacuum tubes in a computer in 1946 (Paul E. Ceruzzi, A History of Modern Computing (The MIT Press, Cambridge, Mass., 2003), 2^(nd) Ed., p. 15).

All that was followed by the basic transistor at IBM in 1947, the stored program in Eckert and Mauchly's 1951 UNIVAC and ultimately putting the data and the program in the same memory with the 1952 EDVAC (Ceruzzi, Ibid.), also bit-parallel arithmetic in the EDVAC, Raúl Rojas and Ulf Hashagen, Eds., The First Computers: History and Architectures (The MIT Press, Cambridge, Mass., 2002), p. 7)), and the use of hardware floating point arithmetic in the IBM 704 in 1955. The vNB was of course carried through in all of these developments.

Then there was the first fully transistor-based computer in 1959, MOSFET transistors in the 1960s, cache memory in 1961, ICs in 1965, active human-computer interaction in the mid-1960s (Ceruzzi, supra, p. 14), the use of semiconductor memory chips in the SOLOMON (ILLIAC IV) computer in 1966, the bit slice or orthogonal architecture in 1972, and LSI for the logic circuits of the CPU by Amdahl in 1975.

The pipelined CRAY-1 with vector registers came in 1976 (R. W. Hockney and C. R. Jesshope, Parallel Computers 2: Architecture, Programming and Algorithms (Adam Hilger, Bristol, England, 1988), pp. 18-19), and finally there were the modular microprocessor-based computers with the Cm* computer of Carnegie-Mellon in 1977 (Id., pp. 35-36), the single chip microprocessor in the early 2000s, and VLSI (16 gates/chip) with the AMT “Distributed Array Processor” DAP 500, in which the memory was placed on the same chip as the logic in 2006, all of which had followed the Babbage path, from which no departure has yet been found. As noted above, the pathway over which those data, both initial and intermediate, and the instructions that selected which of the functions built into the microprocessor would be used at any particular time, came to be known as the “von Neumann bottleneck” (vNB). (von Neumann is not to be blamed for that circuitry, however, since as has clearly been shown innumerable times, it fell to him to be the first to show and describe fully the stored program computer, but not to have initiated the use of a separate data store and the functional circuitry interconnected by busses.)

The procedure described herein, dubbed “Instant Logic” (IL), is represented by entry “C” of FIG. 1, the name coming from the fact that in IL, the desired operations take place the “instant” (i.e., in the first cycle) that and so long as there are data to operate upon, whether internal or external in origin, and then continues on through a “Processing Space” (PS) without interruption into a second cycle, then a third, etc., in a smooth, continuous flow, preceded and paralleled by the code by which the circuitry that executes the successive steps of the algorithm will have been structured. In the course of those operations, new data, if any, are entered as the algorithm may require. Every cycle of operation takes place without effect upon or being affected by any other cycle of operation, whether before or after a particular operation or in the same or a different operational transistor or algorithm. There is no longer any central location to which data must be transferred, or at which the calculations must be carried out, and no instructions are required, but only the independent operation of each operational transistor as such, as it receives data and then acts upon those data in whatever manner it had been so encoded to act.

Now to consider current practice, there are two major efforts being taken to gain greater speed of operation, which center firstly on developing smaller transistors with shorter connections between them and thus quicker response times from both aspects, thus to provide more computing power per cm² of real estate. Another effort is parallel processing, which stands out because in this effort to develop paralleled methodologies as a means of eliminating the sequential processes of the “von Neumann computer,” the principal feature of that computer, what has come to be called the “von Neumann Bottleneck” (vNB), seems to have been left mostly intact. Indeed, if by “Massively Parallel Processing” (MPP) is meant having large numbers of microprocessors all lined up in parallel, and what is then left to do is find a way to have all those microprocessors operate cooperatively, the situation would seem to have been made worse. The use of multiple microprocessors all acting in parallel with one another would in this model seem to have exacerbated that vNB problem rather than resolved it. The gathering together of 100 or so microprocessors entails the introduction of 100 or so vNBs, but the wiring of a network by which those microprocessors are caused to work cooperatively does not add any “Computing Power” (CP), so with the added vNBs and “inactive” network lines the fraction of the effort in the circuitry that is devoted to alphanumeric calculations will decrease.

Applicant's thought then turned to the pass transistor, from which a way in which that vNB might be eliminated came to be suggested. If those pass transistors could be used to structure temporary logic gates using standard operational transistors, with those gates to carry out the desired IP and then be de-structured upon completing whatever arithmetical/logical task had been imposed upon them, then instead of transferring data and instructions to the circuitry that would operate on those data, the circuitry would be transferred to—or rather structured at the locations of—the data. Such encoding—de-coding would run in parallel with but ahead of the data, in a continuous stream, even as the data was passing through the gates that had so been structured and then de-structured, ready for the next IP task to come along. The data itself would flow in the same kind of constant stream as did the code by which the circuits were structured and de-structured, and on the face of it, that process would seem to constitute an enormous leap ahead in the quest for faster and much more voluminous information processing, with any number of algorithms coursing along at the same time. IL is then the result of those musings, made up of the parent patent application hereto along with the present one, in an effort to put those musings into a system that would encompass the concepts derived in those musings.

Considering the array of FIG. 3, the CP of an “IL Apparatus” (ILA) would seem to rest on the number of interconnection opportunities, that relationship arising from the fact that when one wishes to carry out some IP operation, what is looked for is the presence of the requisite number of available interconnection opportunities. One could encode some complex task in different ways, with one encoding scheme yielding a faster response than another, or on the other hand, one that required fewer interconnection opportunities, suggesting that the number of interconnection opportunities would be a rather ambiguous measure of CP. However, the same is true as to determining the CP of current apparatus, in which the same problem can be addressed in different ways of programming. With both methods of conducting IP facing the same ambiguity problem, they can use the same type of solution: current electronics practice would agree (as it has) to use the same standard program to test for the FPS, and IL would use some standard method of encoding the algorithm that likewise measures the FPS.

Turning back now to scalability explicitly, one difficulty with evaluating the presence or not of that feature rests in how to decide what was to be increased in size to determine whether or not the CP had increased accordingly. If the network had to do only with bringing about cooperation between separate processing devices, there is already an inherent problem. In bringing two elements together, that network has only to cause one element to cooperate with another. If then a third element is added, both of those first elements would then have to cooperate with two other elements, and the network would have to be expanded accordingly. Then, with a fourth element added, the network must see to the cooperation of each element with three other elements, and so on—the more the size is increased the more the network must grow, and the less the fraction of the apparatus devoted solely to CP could have grown along with the size of the IP part of the apparatus, so it must be shown exactly what components make up that part.

Consequently, in designing an IL system that would be scalable, there are three features that such a system would need to have: (1) each element would have to be operationally separate from and independent of every other element; (2) each element would need to have its own power and control; and (3) each element would have to interact cooperatively with the other elements as a matter of course, with no more hardware being needed to bring that about. (That there would also be no software goes without saying: the ILA would not recognize a program of instructions, and would not “know how” to deal with one.) Surprisingly enough, such is the case with the IL element of FIG. 2 and the associated power and control circuitry for that element.

In IL, the feature of scalability derives from that fine-grained structure. If the smallest possible operational element that can carry out an IP function is made to be the basic foundation of the apparatus, and is provided with its own power and control, the one aspect of the apparatus that still remains to be shown in order to achieve scalability is that those operational elements would have to operate cooperatively as a matter of course, with there being no need for any additional circuitry, such as a “network” of a parallel processing apparatus, to bring about that cooperation. Individual operational elements of the type shown in FIG. 2 indeed do act cooperatively with one another as a matter of course when they are encoded to do so, as can easily be demonstrated by doing nothing more than simply structuring some binary logic circuits from those elements and then watching their operations.

As to “acting cooperatively,” distinction must be made between what is required to prepare an operational element so as to be put to use, and the actions of some group of operational elements that are acting cooperatively when all of those preparations have been completed, and the elements are in fact being put to use. To take a simple example, in an AND or OR gate scenario, the operational elements involved, which are connected in series and in parallel, respectively, must only act together in response to incoming data so as to execute the respective operations through their cooperative behavior. They do so because the operator, by way of the code, has directed them to do so, so that the respective series and parallel circuits are formed, and that is all that is needed to have that cooperative action take place. If there had been no such code entered, those elements would have had no interaction whatever, since there would be no connection between them. (As an example, each of two such elements, even if adjacent, could be separately encoded as inverters, and here there would be no cooperative action, since there had been no interconnection of those elements that would require such cooperation. Such an operation would yield two outputs, neither of which could have any connection or relationship with either an AND gate output or an OR gate output, or indeed any relationship whatever with what the other element was doing.)

Another “hidden” advantage of IL should also be noted. In current IP circuitry in general, while the processing elements thereof are not vacuum tubes burning up tremendous amounts of energy in their cathode filaments, nevertheless the transistors in the microprocessors will all be on and operating, whether there are programs then being executed or not, and even that will constitute a significant use of power. In IL, no matter how large an array of PSICs there may be, although there will be auxiliary apparatus such monitors, printers, code routers, etc., quietly humming, no electrical power will be getting used up in the PSIC itself unless an algorithm is actually being executed, which in itself should amount to a significant conservation of energy compared even to the quiescent energy consumption of current IP apparatus.

The feature of scalability arises from the fact that the operational elements of the system are individually controlled, without reference to whatever control may be applied to any other operational element, whether distant or “right next door,” and if interpretable as data, positional y significant. When one operational element has been prepared for use, how the next operational element is to be prepared (if indeed it is) is solely up to the operator, e.g., whether to connect a second, adjacent operational element in series with the first in order to structure an AND gate, in parallel so as to structure an OR gate, or etc. The two operational elements will then have become interdependent and would indeed act cooperatively, in either of those circuits or in any others that might be contemplated, but that interdependence would have been imposed by the operator and is a feature of the circuit selected for use, not a feature of the elements themselves.

What may not be readily apparent, and thus remains to be explained, is what the ability to structure binary logic circuits by interconnecting the operational elements thereof has to do with scalability. The answer is that nowhere is it hinted that more elements could not be added, and if the means of so doing (i.e., by adding more processing space through additional interconnection possibilities) uses the very aspect of the ILA that defines its CP, scalability arises as a matter of definition. More exactly, the CP of a PS is measured by the number of inter-element connections that it has available, and the structuring and operation of a binary logic circuit using those inter-element connection possibilities merely corroborates that availability, and likewise corroborates the truth of a statement that such and such PS (and hence ILA) has so much CP.

That is the definition of being scalable: more operational elements can be added at will (of course, if the size of the substrate is such as to accommodate more operational elements), and as more elements would have been added, in that measure alone the CP would have increased in the same fashion and at the same rate. Put another way, the question is whether, in order to increase the CP of an apparatus, there is anything more that one must do than add more of the elements that carry out the IP, in which of course “adding an element” includes adding the circuitry by which an LN 12 could be empowered to operate and then encoded to do so in such and such a fashion. If nothing more is needed, and one is free to add those new elements at will, the apparatus is scalable. In an ILA, the size of the “Processing Space Integrated Circuit” (PSIC), together with the power and control circuitry individually associated with each element thereof, determines the CP of the resultant ILA, and hence is scalable. (In the context of IL, there is no such thing as being “almost scalable,” or that “this device is more scalable than that device,” etc.: a device is either scalable or it is not, and there is no half way or any other fraction. But as will be shown below, scalability can in fact be exceeded, in super-scalability.)

That circumstance may be loosely referred to as constituting a “limited” scalability (which does not contradict the previous parenthetical statement—“scalable” means that the CP is exactly linear with the size of the processing space, but of course one can “nm out of” processing space), since an integrated circuit can only accommodate so many operational elements, but it will be shown below that such integrated circuits can be joined together, also at will (and while so doing bringing out the presence of super-scalability), so in theory there is no limit to the size of a completed apparatus, other than that of cost, power, and space in which to hold the final product.

In order to establish the existence of both scalability and super-scalability, it is necessary to provide precise definitions of (1) “Computing Power” (CP) and (2) “Size.” There are no prototypes of an ILA, so there is no way in which the FPS of any prototype could be measured. However, there is an unambiguous measure of what that throughput must be for any theoretical ILA of some given size. This would not, of course, be expressed in FPS, but rather in the CP potential of a given ILA. The size of an ILA can be expressed in terms of how many PEs it has, where a PE is an operational transistor together with the pass transistors used to structure the desired binary logic gates and the power and control means by which the former devices are made to carry out their IP functions, while the CP of that same ILA can be expressed in terms of how many inter-LN 12 connections it has. As previously noted, the “CP” of a device is not an inherent property, as in having some particular mass, but must be treated as depending upon how it is measured. The basis upon which the above assertions concerning the CP, inter-LN 12 connections, and ILA size were made will be described in detail in the BEST MODE FOR CARRYING OUT THE INVENTION.

SUMMARY OF THE INVENTION

The present application is concerned with the scalability and super-scalability aspects of IL. In order then to apply these properties to the “IL Apparatus” (WA) it will first be necessary to define those terms exactly, starting with the meaning of the term “computing power.” A common measure of that term is the number of floating point operations per second (FPS) that an information processing apparatus, or computer, can carry out. A general definition of being scalable is that the computing power of an apparatus having that property will double if the size of that apparatus is doubled. That definition can be expressed in more common mathematical terms by the assertion that the computing power varies linearly with the “size” of the apparatus or computer, which then leaves the task of specifying how that “size” is measured.

On the other hand, the crux of the present invention is simply that scalability derives from the fact that the basic “Processing Elements” (PEs) that make up the ILA as a whole (1) contain within themselves the entirety of the total “Computing Power” (CP) that may be present in the ILA at any given time, and (2) operate in complete independence of one another. The operating portion of the WA (see FIG. 3) is made up solely of some number n of PEs that may have zero, one, or two connections to a neighboring operational element. It would then follow that CP=kΣp, where k is a constant and p is the computing power of a single connection.

Then, while the scalable aspect of IL derives from the independent nature of the basic PE, the super-scalability of IL derives from the architecture of those PEs. To increase the size of an IL apparatus is really to increase the number of those PEs, but as it turns out, by a simple rule of geometry that architecture will increase the number of inter-operational element connections at a faster rate than that by which that size is increased.

It was noticed that the basic processing element that had been conceived for the purpose of eliminating the vNB turned out to be a PE of which the operational part is shown in FIG. 2. The remainder of the PE would have to lie in separate power and control circuitry that would most assuredly operate in complete independence of any other such circuitry, and by that observation scalability in the ILA was born. The key to acquiring scalability was to avoid having any circuitry that was shared with any other operational part of the system. An exception to that rule is that the circuit that specifies the location of the particular LN 12 to which the particular set of codes is to be applied must of course connect to the pass transistors associated with all of the LNs 12 in order for the code appropriate to the pass transistors of that one particular LN 12 will be reached.

Then in developing from the circuit of FIG. 2 the 5×5 array of FIG. 3, and noting where and how the actual operations would be carried out, which was by way of inter-LN 12 connections, it was noticed that the number of inter-LN 12 connections would increase faster than did the number of LNs 12, and by that observation super-scalability was born. The only way in which that could occur would be by means through which lines that had not been able to make any inter-LN 12 connections would acquire the ability to do so.

It can be seen in FIG. 5 that an operating transistor in IL has two possible ways of forming an inter-LN 12 connection, and that is through the upward and rightward (or “1” and “2”) groups of pathways, since the “3” and “4” pathways are input lines that would be counted with the LN 12 from which they are connected. Super-scalability arises when one “Processing Space Integrated Circuit” (PSIC) is joined to another along the cut lines by which the PSIC is formed, with the LNs 12 through which that joinder is made gaining computer power (cp) through that joinder.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1. (Sheet 1) The IL concept compared to the Babbage method and to current practice.

FIG. 2. (Sheet 2) The basic IL circuit.

FIG. 3. (Sheet 3) A 5×5 array of LNs 12 and associated PTs.

FIG. 4. (Sheet 4) Determination of IN_(j).

FIG. 5. (Sheet 5) Overhead view of a corner of a PSIC 18.

FIG. 6. (Sheet 6) Rightward connections.

FIG. 7 a. (Sheet 7) Conventional Wire Connection.

FIG. 7 b 1 (Sheet 7) Horizontal IL BYPASS Gate.

FIG. 7 b 2 (Sheet 7) Vertical IL BYPASS Gate.

FIG. 8 a (Sheet 7) Conventional BRANCH Circuit.

FIG. 8 b (Sheet 7) IL BRANCH Gate.

FIG. 9 a (Sheet 8) Conventional NOT Gate (Inverter).

FIG. 9 b (Sheet 8) IL NOT Gate (Inverter).

FIG. 10 a (Sheet 8) Conventional AND Gate.

FIG. 10 b (Sheet 8) IL AND Gate.

FIG. 11 a (Sheet 9) Conventional OR Gate.

FIG. 11 b (Sheet 9) IL OR Gate.

FIG. 12 a. (Sheet 9) Iconic version of a Conventional SR flip-flop.

FIG. 12 b. (Sheet 10) IL SR flip-flop.

FIG. 13. (Sheet 11) Corner of an IL PSIC 18 showing interconnection terminals.

FIG. 14. (Sheet 11) Conventional iconic XOR gate.

FIG. 15. (Sheet 12) IL XOR gate shown crossing between two PSICs 18.

BEST MODE FOR CARRYING OUT THE INVENTION

In 2004, in “A Perspective on the Future of Massively Parallel Computing: Fine-Grain vs. Course-Grain Parallel Models,” Proc. CF '04, Apr. 14-16, 2004, P. T. Tosic proposed that instead of having an “evolutionary” (pp. 488-489) advancement in the IP art along the same general principles as he then saw them, what was needed was a “revolutionary” (p. 489) advancement into “new parallel computing frontiers.” The issue was of course the “von Neumann bottleneck” (vNb), J. Backus, “Can Programming be Liberated from the von Neumann Style? A Functional Style and its Algebra of Programs,” Comm. ACM, pp. 613-641 at 615, August, 1978, that has been a concern in the IP art for some 180-odd years (as will be shown below).

This author suggests that the present text provides that “new frontier,” and sets out a new approach to IP that starts out in the electronics art at the most fundamental level possible, and is evidently the first discussion to elucidate both the origin of that bottleneck and then the means by which to eliminate it. The common sense practicality of that solution then brings out advantages beyond that simple elimination of the vNb, that turn out to be inherent in the resultant architecture, and that somewhat astonishingly could lead also to an Information Processing Apparatus (IPA) of essentially unlimited power and scope. That device is the “Instant Logic Apparatus” (ILA).

To carry out any kind of IP, the first essential element, that is designated herein as an “Operational Joinder” (OJ), is to bring together the data to be operated upon and the apparatus that will carry out those operations. To effect that result there are only two possible ways: by sending the operands (the data) into specific locations within that apparatus where the circuitry that could operate on those data is located, as done by Babbage and everyone else ever since, or by providing the “processors” (operators) that will operate on those data at the location(s) of those data. That first historical OJ procedure is of course the origin of the vNb—sending data and instructions to the required circuitry and then back to memory, etc., and the computer industry has been burdened with that procedure ever since.

To eliminate the vNb, IL simply reverses the Babbage/von Neumann paradigm and provides the operators (or, more exactly, the requisite circuitry) at the site(s) of the data. The places within a “Processing Space” (PS 10) at which the WA operator wishes to have the IP take place is then identified as those at which the data will appear, wherever that may be, and will then identify those same places for the structuring of the required circuitry. Operationally, the code for structuring that circuitry will be entered just before the data are caused to enter PS 10. (A table of the components and the number codes attached thereto is provided at the end of this text, just before the claims.)

There is thus no need to send the results of that first operation anywhere, since the circuitry needed for the next step in the algorithm will already have been structured just before the creation of those resultant data, and would then be facing directly onto the circuitry that would participate in the next step of the algorithm. There will then be a continuous flow of code that will structure new circuitry on each step, followed by new data, thus to carry out the IP in a continuous, uninterrupted manner. By way of that circuit structuring, the PS 10 will provide all of the “data-relevant” circuitry needed, by which is meant the circuitry that has data bits passing through the terminals thereof. By data “passing through” is of course meant the input data and then whatever those data may be changed into, joined with, and so on, through the full course of executing the algorithm. Those circuits may be made to wend their way through the PS 10 in directions that the user can select arbitrarily, proceeding in circles or across and down the PS 10 like a typed paper, except that upon reaching a side of the PS 10 the structuring may drop down a row and then be carried back in the reverse direction, thus to “zig-zag” over the PS 10.

Regions of the PS 10 that had just been used in circuits can be put to other uses at once, however the algorithm may require, thus insofar as possible to keep as much of the area of PS 10 at work structuring new circuits as possible, perhaps carrying out some number of similar, parallel operations on some large array of data requiring the same treatment. In any event, the complete execution of the required algorithms in the least amount of time will rest on the ingenuity of the user, but at the end will yield the results needed, after a length of time that should be considerably less than would have been required using current von Neumann computers, even if those von Neumann computers had been using “Massively Parallel Processing”: every time one adds another microprocessor to a system one has also added another von Neumann bottleneck.

(It should be evident that the critical remarks herein concerning “Massively Parallel Processing” are directed solely towards apparatus that use CPUs and microprocessors, and exhibit the vNb; an “Instant Logic Apparatus” (WA) is nothing if it is not “Massively Parallel”—as mentioned several times herein, it is intended to have the entire processing space of the ILA “packed solid” with as many algorithms in the process of being executed in parallel as space allows, all operating simultaneously, which may not quite fit the definition of “parallel” that applies to CPU-based apparatus, but it does fit the common meaning of the term.)

(Given the objective of having as much of the PS 10 “real estate” in operation at the same time as possible, and considering that such goal may require as wide a variety of inter-LN 12 connections as possible, it may be wondered why, in FIG. 2, there are no GA-to-SO or SO-to-GA connections. The reason is that in writing out the code for every type of binary logic gate known by this author, and also all of the basic ADD, MEMORY, and other such circuits, in no case was it found necessary to call on either of those two kinds of connection. If they were never to be used, there would be no point in wasting real estate and fabrication costs in including such connections, so they have simply been left out of the IL design.)

Besides the code itself, what is further needed for the operation of the ILA is the circuitry by which that code causes the desired PTs to be enabled, starting with the process of locating the particular LN 12 to the PTs of which the code that follows will be applied. All of that circuitry has been shown and described in detail in the parent application, which has been incorporated into the present application by reference as expressed earlier, and thus does not need repetition here. The circuitry to be shown hereafter will entirely be circuits that have been structured by the application of the code. The following description of the code has also been provided in that parent application, but the demonstration of scalability and super-scalability rests on specific applications of that code, and for convenience, the code is provided here so as to be close at hand. (The ID numbers used may vary somewhat from application to application, but that should present no problem so long as the code being used relates to the application at hand.)

To bring all that about will require mastery of the code first, and then the circuitry to be structured using that code. The former task requires first the code identification of the components of which the circuit of FIG. 2 is constructed, and these are set out in the following Table I:

ID No. Element Connection 10 PS — 12 LN — CPT1 DR to V_(dd) CPT2 GA to I/O CPT3 SO to GND 14 SPTs 16 I/O 18 PSIC 20 DR 22 GA 24 SO 26 PED 28 DR Signal Line 30 GA Signal Line 32 SO Signal Line 34 IN_(j) Locator 36 LI_(i) Entry 38 +/−₁ Entry 40 XNOR 42 Reference Register 44 r_(i) Entry 46 +/−₂ Entry 48 XNOR 50 RR 52 k_(i) Entry 54 x_(M) Entry 56 Multiplier 58 IN_(j) Output 60 Top Entry Aperture 62 Contact Pin 64 Contact Aperture (As described in the parent application, there can also be an embodiment that has a second physical level of PS 10 aligned above the first level, and reached through a Post controlled by a “Post Pass Transistor” (PPT) that connects like terminals in the two levels using at least one terminal, but that embodiment is not further addressed herein.)

For purposes of clarity in the drawings, the imposition of a code that will enable the desired PTs is shown and described in the figures simply as “1” bits, but the actual process in fact is to apply an enabling voltage sufficient to render conductive each relevant PT of each LN 12 in a circuit that was to participate in the particular step then at hand. That voltage is removed when the circuit has completed its operation on the data for that step, i.e., each of some number of the data bits that had come in to the one or more LNs 12 that were to participate in the particular step of the algorithm, either as initial input or as a result of the operation of a preceding LN 12, had been fully processed, with some resultant one or more bits then passing on to the next LN(s) 12.

If the same function was to be carried out repetitively, as in adding a column of numbers, to accommodate the continuing arrival of new data bits the PTs so enabled could simply be left in that conductive state until the complete data stream had been operated upon. That process would be carried out with respect to whatever amount of circuitry would be common to whatever sequence of numbers was to enter as input, and likewise at any other location within the algorithm at which repetitive processes were to be carried out, or as to any other repetitive function than addition.

One reason for using that fixed voltage source is to ensure that with issues of fanout sometimes arising, the voltage would suffice to enable every PT as needed for a circuit. A second reason is to avoid problems of logic racing. As will be seen below, there is one place in the XOR gate where two signal sources serve as inputs to a 2-bit output AND gate and hence must arrive at the same time, but the pathways followed in reaching that AND gate differ between the two branches. To use a “1 bit” (i.e., that applied voltage) of too short duration leaves the possibility that the “1” bit (if any) on one side would have begun to decay by the time that the other “1” bit (if any) had been received. In this and other similar circumstances, some “fine tuning” of the process might be required.

A Toggle flip-flop (not shown) could be used to turn on the enabling voltage when the code therefor had been received, then turning that voltage off upon completion of the operation, using a second entry of that same code. The times of those two events would be adjusted so that the enabling voltage would be present on the particular SPTs 14 at the times that the signals reached both inputs to that output AND gate, and in other such similar circumstances (which could be much more complex). It would only be necessary that the signal bits were of sufficient duration to act at the same time, but if necessary the timing and duration of those could also be controlled either by toggle switches or by the clock. It is clear that every complex algorithm would need to be controlled by its own individual clock, which is provided for each LN 12 in any event.

It should be stressed, however, that the manner in which these enabling voltages are handled has nothing to do with the speed of operation in carrying out IP, but only with maximizing the amount of available PS 10 space, and thus to affect the throughput only indirectly, i.e., more space taken up by LNs 12 with enabled SPTs 14 that were not yet in use would mean fewer algorithms in operation. The circuitry for an algorithm could have been structured in advance of the operation, and simply have been left available, so what is at stake is simply the question of how little PS 10 space could be used for the algorithm, thereby to “free up” as much space as possible for other algorithms.

The questions are: (1) how soon before any data arrive must the codes that would structure the circuitry that would operate on those data be entered; and (2) how soon after the data have arrived can the enabling bits that had structured the required circuitry be removed. The purpose in resolving these issues is again to minimize the amount of circuitry needed to be present as to each cycle of the operation, as well as the length of time during which that circuitry must remain in place. In other words, no more LNs 12 are to be in a “structured state” as part of a circuit at any one time than is necessary, in order that those LNs 12 that need not be structured at each particular time would remain available for use in the circuits of other algorithms. These adjustments would constitute the “fine tuning” of the code, and could be a rather time consuming operation for the user. As to the issue of whether to use a single clock and encode all of the algorithms at the same time or provide a separate clock for each algorithm and execute all such algorithms independently of one another, it is clear that independent operation would be highly preferable, indeed almost essential, in order to permit the timing adjustments and other “fine tuning” exercises noted above to be carried out.

It is presumed that the user, having identified an IP task needing treatment, would have found or developed an algorithm in algebraic form that would solve that problem, and would then, knowing the circuit equivalent of each of the algebraic terms, would have converted that algebraic formula into a “circuit equivalent,” i.e., would have laid out a series of circuits that expressed the sense of all of the terms of the algorithm, and thus would have set out an extensive circuit by which the algorithm could be executed. (The circuit of FIG. 4 and the associated equation provide an example of that process. It remains, however, to encode that equation so that locating all of the IN_(j)s thereof could be carried out in IL.) The development of the SPT 14 enabling code then rests on the user having laid out that circuitry on paper or on a computer screen, whereupon in essence that enabling code fairly “pours out” directly from that circuitry.

What is then required is simply to take a blank PS 10 form (on paper or on screen), i.e., FIG. 3 (in practice, of course, a much larger equivalent), and mark off those SPTs 14 that if enabled would duplicate the circuit drawing just constructed. To develop the code then requires the user only to make note, as to each such SPT 14, the two LN 12 terminals between which the particular SPT 14 extends, and then extract from that information the data set out in Cols. 2-4 of Table II below so as to be able to select out from Col. 5 the correct vector code.

In Table II below, after that first “SPT 14 No.” column (1), the next three columns show (Col. 2) the identity of the terminal on the originating LN 12 (OLN) to which the proximal end of the SPT 14 at the OLN is connected; (Col. 3) the direction from that OLN in which the SPT 14 extends (thereby to identify the receiving LN 12 (RLN)); and then (Col. 4) the terminal of the RLN to which the distal end of the SPT 14 connects. The last two columns show the two codes that could be used (of course with the connections from memory to the PTs on each LN 12 in PS 10 being set up accordingly), with the Vector Code (Col. 5) being that which rests on the identification of the terminals and the direction as just stated, and then the Binary Code (Col. 6) simply uses the binary form of the identification numbers of the PTs as shown in FIG. 2. (The Vector Code is used in all of what follows.)

TABLE II SPT 14 OLN RLN Vector Binary No. terminal Direction Terminal Code Code 4 DR 20 Right 01 DR 20 010101 00100 5 DR 20 Right 01 GA 22 010110 00101 6 DR 20 Right 01 SO 24 010111 00110 7 GA 22 Right 01 DR 20 100101 00111 8 GA 22 Right 01 GA 22 100110 01000 9 GA 22 Right 01 SO 24 100111 01001 10 SO 24 Right 01 DR 20 110101 01010 11 SO 24 Right 01 GA 22 110110 01011 12 SO 24 Right 0 SO 24 110111 01100 13 DR 20 Up 10 DR 20 011101 01101 14 DR 20 Up 10 GA 22 011110 01110 15 DR 20 Up 10 SO 24 011111 01111 16 GA 22 Up 10 DR 20 101001 10000 17 GA 22 Up 10 GA 22 101010 10001 18 GA 22 Up 10 SO 24 101011 10010 19 SO 24 Up 10 DR 20 111001 10011 20 SO 24 Up 10 GA 22 111010 10100 21 SO 24 Up 10 SO 24 111011 10101 22 DR 20 DR 20 0111xx 10110 23 GA 22 GA 22 1011xx 10111 24 SO 24 SO 24 1111xx 11000 25 Input/Output

In greater detail now, the leftmost column in Table II shows the assigned number of each of the SPTs 14 as shown in FIG. 2. (The codes for the CPTs were previously shown to be 01 for the CPT1 (DR to V_(dd)), 10 for CPT2 (GA to external input), and 11 for CPT3 (SO to GND), and hence are not shown in Table II.) The last two columns of Table II illustrate the two methods of encoding the circuitry, with that first “Vector” method being based on the information that appears in the second, third, and fourth columns of Table II, and then the binary method simply using the binary version of the assigned SPT 14 numbers given in column 1. The CPTs are not characterized by any appended number by analogy with the “14” for SPTs since their identifying numbers appear as the last entries in their names, i.e., the “1,” “2,” and “3” in “CPT1,” “CPT2,” and “CPT3,” respectively. (That different procedure is used since the two types of elements play different roles, employing circuit code and signal code as to the respective CPTs and SPTs 14.)

In the “Vector” column 5 of Table II, the first two digits express the code for the originating terminal on the OLN (DR=01; GA=10; SO=11) for the proximal end of the SPT 14 line; the next code is two-digit and specifies the direction of the SPT from the OLN to the RLN, rightward=01, upward=10, inward=11, for a 3-D embodiment, but the 1-bit code shown in parentheses in Col. 5 should be used for the 2-D embodiment employed herein, for which rightward=0, upward=1; and the last two digits in Column 5 identify the destination terminal of the RLN to which the distal end of the SPT 14 connects, using the same code as that which was used for the proximal end of the SPT 14, i.e., DR=01; GA=10; SO=11.

The binary code method of encoding the SPTs 14 is simply to use the binary equivalent of the assigned numbers of the SPTs 14 that are shown in the first column. That would also require only five bits, but is not used even so, since the use of that binary method would require the encoder (user) to have a digital-to-binary conversion table at hand (or else develop those codes mentally, which process would be prone to error), while the vector method develops the code directly from looking at the circuit that the encoder is using, if the foresight to write out that circuit had been exercised.

The resultant full code using the 2-D Vector method would then appear as

-   -   iiiiiiiiiicccds₁s₁s₂s₂s₃s₃         for enabling a single SPT 14 on a single LN 12, wherein the         10-bit “iiiiiiiii” code expresses the IN_(j) value of the LN 12,         the “ccc” code expresses the CPT code, “d” is the direction         code, and for a single SPT 14 the code is “s₁s₁s₂s₂s₃s₃”. If two         SPTs 14 were to be enabled on that single LN 12, the full code         would appear as     -   iiiiiiiiiicccds₁s₁s₂s₂s₃s₃s₁s₁s₂s₂s₃s₃.         Of course, the length of the iii . . . “is set to accommodate         whatever the size of the PS 12 being used might be.

Before setting out to encode any PTs, however, it is necessary first to identify the LNs 12 to be used in structuring the circuit. Whatever may be the number of LNs 12 that are involved in a particular step of the algorithm, the code for all of the PTs needed to structure the corresponding circuits involved in that step are enabled at the same time, in a single “Code Line” (CL). As can be seen in the above code, for each LN 12 the IN_(j) code is placed at the front of the code for that LN 12, and then all the CPT, direction, and SPT 14 codes, in that order. After the equivalent of a carriage return (which in this case will put a double space between the codes for separate LNs 12), the IN_(j) code for the next LN 12 involved in that same step of the algorithm is brought in, again followed by the relevant CPT, direction, and SPT 14 codes, with that process then continuing until the IN_(j), CPT, direction, and SPT 14 codes for all of the LNs 12 that participate in the circuitry for that particular step of the algorithm have been assembled into the CL for that step. The CL is then dumped as a whole into memory (specifically, a “Code Cache,” which is preferably separate from the main memory). Preferably, a “test run” on the CL would be run before the CL was saved in that Code Cache for future use.

As noted above, where in the PS 10 the circuitry will be structured for an algorithm can be anywhere that would not already be in use at the same time, but even so it is necessary to establish the “Index Number” (IN_(j)) for entry (as the first part of a CL) when the encoding is to take place, with those IN_(j) being the binary versions of the “Location Indicators” (LI_(i)'s) assigned to each LN 12. In the gross 5×5 array of LNs 12 shown in FIG. 3 (which was formed of so few LNs 12 in the figure simply so as to have readable sizes of those LI_(i)'s in FIG. 3), the LI_(i) are shown just below and to the left of the “Operational Transistors” (OTs), which are shown by large circles with an “Index Number” (IN) label in the center thereof, and the LI_(i) are seen to increase in value going left to right and then downward when switching to a new row. Instead of the tiny PS 10 space shown in FIG. 3, in practice there would be as many LNs 12 on a PSIC 18 as would render it still possible for connections of the enabling voltages to be made to the PTs.

INj Determination

Absolute LI_(i) value determinations. Generally speaking, it would be easy enough to establish the x, y, and z coordinates of an LN 12 that was even deep down within the PS 10 somewhere, but by itself that would not disclose the LI_(i) value. Even so, an LI_(i) value can easily be found from those coordinates. Since the x, y, and z coordinates can be found by inspection, the LI_(i) can then be found from the following equations, wherein the LI_(i) values are based on absolute terms, i.e., solely on the specific coordinate values of the LN 12. (If the following equations are solved by a computer then the terms therein will necessarily be in binary form already, so to get an actual LI_(i) value as literally shown in the equations would require conversion back from the binary form, but since it is the binary form IN_(j) that is ultimately being sought in any event, one can simply ignore that added process and simply take that IN_(j) value as it will naturally emerge from the calculation.) The following equations will of course be very similar to those used in the “Relative LI_(i) value determinations further below:

For a 1-D array,

LI_(i)=LI(x)=x,  (1)

where x is the coordinate of the LN 12 for which the LI_(i) value is being sought.

For a 2-D array,

LI_(i)=LI(x,y)=X _(M)(y−1)+x,  (2)

where X_(M) is the length of the x axis and x and y are the coordinates of the LN 12 for which the LI_(i) value is being sought. The row in which the reference LN 12 is located has the value y=1, so a point that was in that same row would not involve the addition or subtraction of the X_(M) row length, but a point in one row downward would add the full length of that row, and then any further displacement of the “target” LN 12 would be added, as indeed it should to get the correct LI_(i) (and thus the IN_(j)) value. That is, the originating row is row 1, one row down is row 2, so X_(M) (y−1)=X_(M)(2−1)=X_(M), and the result would become LI_(i)=X_(M)+x. More generally, LI_(i)=±kX_(M)±x, where k is the number of rows down (or up), where down is positive and up is negative.

For a 3-D array,

LI_(i)(x,y,z)=±X _(M)(Y _(M)(z−1)+y−1)+x,  (3)

where X_(M) is again the length of the x axis, Y_(M) is the length of the y axis, and x, y, and z are the coordinates of LN 12 for which the value is being sought. In this case, a z value of 2 would add in the product X_(M)Y_(M), which would be the LN 12 content of one full plane of LNs 12. The “±” term is used as before, if either X_(M) or Y_(M) is leftward or outward, respectively.

(Rather than use the equations, in using a computer it might be worthwhile to have prepared tables in which the LI_(i) values were filled in for all of the x, y, and z coordinates of a PS 10 of each size that your institution uses. The IN_(j) values could also be shown, although their length might preclude having a readable graph, especially if the PS 10 were 3-D, and very large.)

Relative LI_(i) Value Determinations: Those LI_(i) values can also be found from the positions of the LNs 12 in question relative to an LN 12 for which the LI_(i) value is known. This procedure is important in the development of “Code Modules” (CMs) that will provide the code necessary for the structuring of as many different circuits of a particular type as may be required. (The same applies also within functions such as addition, where there will be partial sums scattered all over the PS 10, thus to require the insertion of a good many repetitions of a half-adder and the linkages between them.) Such a CM will have been developed using some particular set of input LI_(i) values in an exemplar circuit, but when using that CM, as a rule the LN 12 locations at which the circuit needed to be structured would be different. Using the formulae given below, the code for the desired circuit can be obtained by having prepared a set of those formulae for each circuit type to be structured, wherein the constants X_(M) and Y_(M) in the formulae would have been taken from the dimensions of the PS 10 then in use, so the full code for the desired circuit (for each step of the algorithm) can be determined simply by identifying the circuit type and entering a LI₁ reference number.

The relevant parameters (defined below) are picked up out of the CM data used in the formulae below and taken in hand for each LN 12 of the particular circuit, as specified in the CM. By such means, various versions of the circuit could also be selected by way of additional indicia beyond just the name, e.g., in selecting whether the circuit was to extend in the horizontal or vertical direction, whether continuously or should turn off at some point, and as a result there would be different directions in which to proceed within the circuit itself, thus to take account of whatever space constrictions might arise from there being other circuits present for other algorithms at the time that the circuit that was then to be structured was needed.

(Needless to say, the circuit that had been “drawn out” for use in developing the code therefor would preferably have an electronic version, along with electronic versions of whatever circuits for other algorithms were then present (or were about to be), so that the circuitry then being built up could be mapped around those circuits. Those other circuits for other algorithms would of course need to be changing with each click of the clock, since each click would signal the need to structure a new set of circuits for the next step of the algorithm.)

It should be noted that where there appears to be a “collision,” i.e., where the LN 12 that one would like to use is already in use at the time in question, that usage may disappear on the next cycle. Each “mapping” of the LNs 12 to be used should then be tied to a particular time frame, since a shifting in time may make a desired circuit structuring of the algorithm then being mapped perfectly possible, where by “mapping” is meant the identification of all of the LNs pertinent to a cycle of the particular algorithm or part thereof. In other words, collisions may be avoided by a shift by either the algorithm then being encoded or the algorithm already encoded, in both space and time. A delay in the completion of some particular cycle need not delay the ultimate output time unless the branch of the calculation sought to be delayed was already the slowest branch.

Using one CM rather than another (for the different versions of the circuitry to be structured) would result in different values for the relative locations of the LNs 12 that a particular CM had defined, but regardless of which CM was used, the relative formulae would remain as follows:

For a 1-D array,

LI_(i)=LI₁±r_(i),  (4)

where LI₁ is the reference LI_(i) value and r_(i) is the distance along the x axis, in either direction away from the location of the reference LI₁, of the LN 12 for which the LI_(i) value is being sought.

For a 2-D array, moving up or down subtracts or adds a number to the LI₁ that is equal to some multiple of that row length, depending upon how many rows away from the reference LN 12 that next LN 12 was located, i.e.,

LI_(i)=LI₁ ±r _(i) ±k _(i) X _(M),  (5)

where LI₁, r_(i), and x _(M) have the meanings as before and k is the number of rows above or below the row containing the reference LI₁ in which the LI_(i) in question is located.

For a 3-D array, for a location that is one or more planes away from that which contains the LI₁, for each plane moved away there must also be added or subtracted the area of a plane in the array, i.e., X_(M)Y_(M), thus to yield

LI_(i)=LI₁ ±r _(i) ±k _(i) X _(M) ±m _(i) X _(M) Y _(M),  (6)

where LI₁, r_(i), X_(M) and k_(i) have the meanings as before, Y_(M) is the length of the y axis, and m_(i) is the number of planes along the z axis by which the LI_(i) in question is removed from the original plane of the reference LI₁.

When using a step-wise manner of determining the LI_(i) for the LNs 12 involved in the algorithm, there are two ways in which to proceed: (1) using the same LI₁ as the reference throughout all of the steps of the algorithm and for all of the sequential data; or (2) when obtaining a new LI₁ value following each one step of the algorithm, and then using that new LI₁ value as a new LI₁ reference. If the original LI₁ were used as the reference throughout, the LI₁ values could be anything, and would depend both upon how far away in the circuit the particular LN 12 was located, and how far that circuit had been displaced. The complete Eq. 6 would then have to be used. If using the new LI₁ reference, the numbers away from that reference would be smaller and easier to accommodate, but would require a mind wrap to get rid of the original LI₁ mind set. Either way would have its error traps, and these would have to be overcome, but could be with just a bit of concentration.

The question then arises: what does all of that have to do with scalability and super-scalability? The long answer is that the above formulae can be used for at least five purposes: (1) to determine the LI_(i) and hence IN_(j) values of the remaining LNs 12 in a circuit based on a drawing of that circuit, using the value of an arbitrary one of the LNs 12 of that circuit (typically one of the inputs) as a LI₁ reference; (2) to track the course of additional instances of a circuit based on there being some repetitive process, as in the successive half-adders in an ADD process; (3) the development of a library of CM for some set of standard circuits for future reference purposes; (4) tracking of the sequential steps of an algorithm to identify where the next LNs 12 can be put to use; and lastly (5) reconstructing the values of IN_(j) when an additional PSIC 18 was or was to be joined to an existing PSIC 18. It is in this last process that super-scalability is found. It is not found in new, unexpected LNs 12, but rather in LNs 12 that were able to make inter-LN 12 connections that had not previously been possible.

It is not the purpose here to describe the details of those first four processes, which are not directly relevant to the present issues as to which claims are made, but only the last. What has been said so far, however, will be needed in order to recognize the way in which super-scalability comes about, so that subject will now be addressed.

In a 2-D environment, any circuit to be structured by IL can be defined by setting out the r_(i), k_(i), X_(M), and m, values that are applicable to each LN 12 within the circuit (and within the PSIC 18), and such a collection of those values for all of the LNs 12 involved in each step of the circuit will constitute a CM. Values can be identified for all of the LNs 12 that are parts of some particular circuit, or for another new, identical circuit that is displaced from an initial circuit. With that information, it is not necessary to have any knowledge of the circuit being structured, but in addition to that information one must only know what was the LI₁ value from which those r_(i), k_(i), x_(M), and m_(i), values were found. It then only becomes necessary to express those values in binary form and carry out those calculations, while assuring that the “iiiiiiiiii” value that results remains associated with the code that defines each SPT 14, i.e., the “cccdssssss . . . ” code as had been associated with the original LI₁.

Once all of the “iiiiiiiiii” codes for the circuit LNs 12 have been determined, any movement of the circuit, or more likely, a repetition of the circuit at another location, would have “moved” every LN 12 in the circuit by the same amount, so by using that fact repetitive calculations relative to the IL₁ location can be avoided. However, motion being relative, displacing a circuit is equivalent to re-defining the system by which the IN_(j) are specified, which is what usually happens when one PSIC 18 is joined to another PSIC 18, as seen in FIG. 15 (Sheet 12), which shows an XOR gate being structured across the “Processing Space Cut Line” (PSCL) between one PSIC 18 and another. (To obtain the correct LI_(i) numbers, adding another PSIC 18 at the bottom of one original PSIC 18 is an easy process, since then one only needs to continue counting, but when adding one to a side requires a redefinition of the IN_(j) values nearly all across the original PSIC 18.) What now follows is a description of how that can come about, and of the tasks that a user faces when it is decided to add another PSIC 18.

If initially installing an algorithm, the above-listed values would be entered “by hand,” based on the structure of the circuit as drawn out on paper or preferably on screen, and determining therefrom the r_(i), k_(i), and m_(i) values for use along with the LI₁ and x_(M) values, the former of those last two being selected by the user (on the basis of which circuit is to be structured and where there is space enough to structure that circuit) and the latter being set by the x dimension of PSIC 18. If using a CM, the X_(M) value would already be contained within that module, and it would only be necessary to enter the LI₁, r_(i), k_(i), and m_(i) values appropriate to the first LN 12 of the circuit, and then a code sub-routine would have been set up to calculate the location of each of the other LNs 12 of the circuit relative to the position of that first LN 12. The locations of the LNs 12 of a circuit being moved could be determined by applying the applicable one of Eqs. 4-6 to each of those LNs 12 using the same LI₁ value, i.e., by determining the different r_(i), k_(i), and m_(i) values that each LN 12 would have by virtue of having different positions within the circuit, or preferably by applying a single LI₁ value to obtain a reference LI₁ value as to one of the LNs 12 in the circuit, and then using those equations again with that LI₁ value serving as the reference, along with the structure of the circuit, to obtain the LI_(i)=LI₂, LI₃, etc., and then from those the IN_(j) values for the rest of the LNs 12 within the circuit. (Of course, if the equations were executed in the computer, using the circuitry described below and not by hand, all of the terms would already have been converted to binary, and it is not an LI_(i) that would emerge from a calculation but a binary IN_(j).)

FIG. 4 (sheet 4) shows in block diagram/icon form an “IN_(j) Locator Circuit” (ILC) 34 by which all of the IN_(j) values for a circuit can be calculated as just indicated. The steps to be followed in using that circuit are shown in FIG. 4 by sequential numbers linked by arrows to the relative points in the diagram. As noted earlier, by the terms used in FIG. 4 what had been referred to initially as the LI₀ LN 12 reference point has now, in this algebraic context, become LI₁, since it is the first of the LNs 12 that make up the circuit itself.

FIG. 4 is drawn for a 2-D embodiment of the PSIC 18, and hence Eq. 5 is used, and the circuit of FIG. 4 is so structured. The variables are entered in the order shown by the numbers connected by arrows to the various points. The LI₁ value is thus entered first, as shown by the numbers “1”on each side of the circuit at an “LI_(i)” field 36 (labeled “LI₁,” with the connected reference number 36), and it is then seen that within the circuit that LI_(i) value effectively enters on both sides of the circuit, since it is not yet known whether an addition or subtraction will occur. Although two “LI_(i)” fields 36 are shown in FIG. 4, in fact there is only one physical blank field so labeled, and only one manual entry of an “LI_(i)” value is carried out, with the two of FIG. 4 being shown in order to have such a field available in both the ADD and SUB sides of the drawing, of which only one will be connected in as a result of the “+” or “−” entry in step 2. (No actual circuit such as that of FIG. 4 need be structured in order to carry out IL, since that circuit is not necessarily a part of the IL circuitry, but even so the circuit drawing itself should aid one who wishes to practice the art of the processes involved, even if done “manually.”)

Which of those two sides down FIG. 4 will then actually be followed in the circuit depends upon the second entry, which will be entered as either a “+” sign or a “−” sign at the top of the figure labeled “2,” with the path to be taken then depending on the location of the second LN 12 of the circuit relative to the first, as expressed in Eq. 5. That “2” field is labeled as the “+/−₁” 38 field, with that “1” subscript being present because a second “+/−₂” field will be employed later.

That “+/−₁” 38 entry point connects to one input of a 2-bit XNOR gate 40 on each side of the circuit, with the second input to XNOR gate 40 connecting to a “Reference Register” (RR) 42. As it serendipitously happens, one of those RR 42 can hold the ASCII code for a “+” sign and the other the ASCII code for a “−” sign, since these differ only by the “+” code having a “01” in the third and second leftward positions, while the ASCII code for a “−” sign has a “10” at those two positions. (When employing the blank fields of the formula, the user will follow the easy path and simply enter either a “+” or a “−” symbol just as it appears in the formula, given that only the two bit positions indicated are needed to distinguish between the two.) The particular XNOR 40 gate for which the RR 42 code and the code entered at the +/−₁ 38 entry point are the same will yield a “1” bit, thus to select either the “Addition” (ADD 44) circuit or the “Subtraction” (SUB 46) circuit. This first step serves only to select which mathematical formula will come to be used, i.e., which of the two alternative versions of the first step of Eq. 5 will be used, and nothing else will occur until what turns out to be either a subtrahend or an addend is entered in the third step.

(This procedure is not the most efficient that could be used, but has been designed to be as “user friendly” as possible, which was thought to be that procedure in which the user need only have the above Eq. 5 (in this case of a 2-D PSIC 18) at hand (preferably in an on-screen list, where the correct entry need only be copied and then pasted into an empty, properly labeled blank field, with a copy of the circuit drawing also being displayed), with all of the OTs labeled by those left-to right, top-to-bottom LI_(i) numbers, and then enter in succession the terms of that formula just as expressed therein. Again, this process is intended for use only in the initial installation of an algorithm “by hand” from a circuit drawing, while in using a CM more efficient electronic means would be used.)

In step 3 the r_(i) value, as the next term in the equation, is entered at another blank field, as shown by the term “r₁” and the label “48” on both sides of the circuit and labeled by a “3,” which connects to both of the r₁ entry points, the respective outputs of which are shown to be LI₁+r₁ or LI₁−r₁, depending upon whether “+” or “−” had been entered at location 38 in Step 2. As in the case of the LI₁ entry, there is only one blank field, this time labeled “r₁,” and only one physical entry will be carried out, but the value entered will appear in both the ADD and SUB branches on the two sides of FIG. 4, but of which only one will be connected in, depending upon whether a “+” or a “−” had been entered. Ideally, the side not used would dim out to half intensity.) With the LI₁ value having already been entered into both the ADD 44 and the SUB 46 circuits in step 1, but only one of those circuits will have been enabled, so in this first part of the FIG. 4 figure upon that “r_(i)” being entered as indicated by the circuit drawing, that will show the distance r_(i) of the LN 12 next to be located, and either the “LI₁+r_(i)” or the “LI₁−r_(i)” value will have been found. (At this stage, the screen should only show the LI₁ value, either the “+” or “−” symbol, and now the r₁ value, with the “+/−₂” field still remaining blank.)

It should be noted that the lines that connect to the outputs, if any, of both the ADD 44 and the SUB 46 sides are bidirectional, as shown by the double headed arrows. As a consequence, if the first operation had been an ADD 44 to form the quantity LI₁+r₁, that quantity will be transferred both to that second ADD 54 and to that second SUB 56. That is necessary because the second operation of an ADD 54/SUB 56 pair could just as well be a SUB 56, and without that bidirectional transfer there would be nothing on that second SUB 56 side from which to subtract that k_(i)x_(M) value, and similarly if the first operation were a SUB 56 and the second an ADD 54.

In the next part of FIG. 4, either a “+ or a “−” is again entered in step 4, at the second “+/−₂” 50 entry point. The operation with respect to a pair of XNOR gates 52 and a pair of RRs 54 is the same as before, and in this case, since this circuitry is invisible to the user and with the earlier XNOR 40 gates and RRs 42 having finished their tasks, there is no reason not to use those same XNOR 40 gates and RRs 42 a second time, even though they are shown as new elements in FIG. 4. (Again, these are not special circuits built for this purpose, but rather operations carried out through the software written for application to the calculating function of the apparatus as a whole. The circuit symbols are used simply to provide illustration of what the software is doing.) Whichever way that may in fact be done, that one of the “+” or “−” symbols that would comport with the form of the circuit to be structured is entered into the indicated field, and in that same manner either an ADD 56 or a SUB 58 circuit would have been enabled, consistent with the symbol that had been entered.

Now unlike the first determination in which the quantity to be added or subtracted was entered immediately after the selection between those two operations was made, in the present case the quantity to be entered must first be calculated. As a consequence, there are actually two next steps, the fifth and sixth steps in the terms of FIG. 4, which steps consist of the entry of the quantities k_(i) 60 (the number of rows, of any, by which the LN 12 in question is displaced from the row holding the reference LN 12) and x_(M) 62 (the maximum value of the x axis), with k_(i) 60 having been learned from the circuit thawing and x_(M) 62 from the size of the PSIC 18.

As the next steps in the FIG. 4 sequence, the values of “k_(i)” and “x_(M)” are entered into a multiplier 64, again by appropriate labeled blank fields for the respective “k_(i) 60” and x_(M) 62″ values, and the product “k_(i)x_(M)” that would immediately be calculated is passed on up to both of the ADD 56 and SUB 58 circuits. Based on which of those two circuits had been enabled, i.e., the ADD 56 or the SUB 58 operation as to an LN_(j) 12 in a different row than the reference LN₁ 12 will be carried out. The first operation may have been an addition and this second one a subtraction, but in any event, the entry of those k_(i) 60 and x_(M) 62 values provides the basis for the completion of that seventh Step, i.e., the execution of the complete formula “LI_(i)=LI₁±r_(i)±k_(i)x_(M)” (66), so the IN_(j) value for the particular LN 12 has thus been determined. The process just described must of course be carried out for all of the LNs 12 for all of the circuits that express the algorithm in order to accomplish a complete execution of that algorithm.

How a user may break up the encoding task so as to know at particular times that “that job” is done is up to that user, but in any event, when a user had located an IN value for one LN 12, the process just described would be repeated for another LN 12 until that task was “done.” The kinds of circuits that would lend themselves to being used as code modules would also be those for which one could develop all of the values therefor and then turn to the rest of the code, so we can assume that such would be the case here, i.e., to make any “breaks” in the job take place upon the completion of the encoding for those LNs 12 that would make up a complete CM.

With the task of encoding the locations with IN_(j) values for some particular IL circuit having been completed, it remains only to extract those IN_(j) values so that they can be joined up with the rest of the code. That constitutes step 7 in FIG. 4 and is so labeled. There will of course be as many IN_(j) values as there are LNs 12 in the circuit (or in the step, if the encoding is being done stepwise, which of course still means getting to the end of each algorithm eventually), which list would be arranged for easy joining with the remaining cccds₁s₁s₂s₂s₃s₃ . . . codes for entry into the CL.

But before getting into the actual circuit structuring, it seems appropriate to take note of a disadvantage of IL, perhaps obvious from FIG. 2, which is that an extraordinary number of off-chip connections will be required on each PSIC. Besides the V_(dd) and GND connections, for each LN 12 there are 18 connections involved with the PTs, which are seven rightward SPT 14 connections, seven upward SPT 14 connections, and three CPT connections for a total of 17 PTs, and then the I/O 16 connection, for a total of 18 top-down connections, or 20 connections in all, including V_(dd) and GND. V_(dd) and GND are connected horizontally through the PSIC 18 itself, however, so that leaves 17 PT connections and the I/O 16 connection for 18 connections to be made top-down. For a 5×5=25 PSIC 18, that would mean 25×18=450 total top-down connections per PSIC 18. A circuit version of such a PSIC 18 is shown in FIG. 3.

There are several limitations on how many LNs 12 could be incorporated on a single IC. It may be noted first off that except for removing the rounded portion of a circular wafer there is no reason for slicing the wafer into chips. To form a PSIC 18 the wafer could incorporate a single IC, since the object, after all, is to have as many LNs 12 disposed on a single square chip as possible, and for that purpose the fewer the cuts the better. (The cutting process itself can introduce faults, besides taking up space.) In order to make that number of LNs 12 as large as possible, there is again the question of how small the transistors can be made, but IL introduces another limitation in how small the hardware that makes that top-down connection can be made. In particular, as will be shown below, the actual connection is made by way of a pin, and there is a practical limit on how small such an element can be made and still be subject to dependable and accurate manipulation for proper placement. That is a matter that can only be determined by experiment, no doubt using a micromanipulator (that would also no doubt be used in the actual fabrication of the PSICs 18), so it is not possible at present to give an accurate estimate of how many LNs 12 could be placed on a chip. (One may surmise, however, that it will be this pin issue and not how small the LNs 12 and SPTs 14 can be fabricated that will place the upper limit on that number.)

The approach then taken to this off-chip connection problem was that “top-down” method of making external connections to the various terminals within the PSIC 18. The structure of the chip itself has been described in detail in the parent application, incorporated herein by reference, but some aspects of that procedure bear directly on the issues of scalability and super-scalability, and hence the topics that relate directly to those aspects of IL are set out herein again, with the relationships to scalability and super-scalability being explicitly pointed out.

It would seem that the issue of scalability had already been encompassed, at least in part. If the operation of an LN 12 (i.e., the SPTs 14 associated therewith) depends only upon the code sent thereto, and each LN 12 has a full contingent of its own code arriving thereto, each LN 12 will then operate fully independently of any other LN 12, with all of the power necessary for full IL operation. Of course, the fully independent LNs 12 have to work together if any IP is to be carried out, but that kind of cooperation is a function of the algorithms and the user's choices, and is not anything inherent in the PSIC 18 itself. There is a limit to the size to which a PSIC 18 can be built, however, so while the independent operations of the LNs 12 suffice to establish at least a “limited” scalability, it remains then to eliminate that limit.

A way to do so would be through the joining together of as many “basic” PSICs 18, by which is meant a PSIC 18 of some convenient fixed size that could be replicated without limit, and then be joined up together as far as one wished to go. If by way of such joinders more and more fully operable LNs 12 could be added to an existing PSIC 18 at will, then IL, would again show itself to be fully scalable. The viability of that statement would depend upon the fact that independent encoding circuits exist for every LN 12 in each of those basic PSICs 18, so suffice it to say, as shown in the parent application, that every LN 12 has associated therewith a complete and independent array of encoding circuits, so an unlimited scalability would seem to have been shown.

For actually reaching each of the LNs 12 in an array, in order to avoid having to search through an excessive number of LNs 12 in order to find a particular one, the circuit that carries out that task was described in terms of an array having 32 LNs 12, which was used as a sort of mean-sized PSIC 18 to act as a PSIC 18 module (but mostly to make a size of PSIC 18 as shown herein in which the labels of the parts thereof would be readable in the published version of the patent). That size of 32 could easily be increased to 36 or reduced to 25 in order to have a square PSIC 18 for easier determination of IN_(j) values. For purposes at present, a 5×5=25 PSIC 18 (for which the transistor array is shown in FIG. 3) will better fit into that readability factor, and also the matter of future calculations, so then to locate an LN 12 having any IN_(j) then requires only that the correct CM be used, by way of a preceding module code, e.g., “A, B, C, . . . ”. It is evident that one could use up the fall alphabet, then start with two-letter preceding code, then three, then back to numbers, etc., wherein, e.g., the code E11 would mean the 11 LN 12 on the E CM, or XZ22 would be the 22^(nd) LN 12 on the XZ CM.

With that issue in mind, FIG. 5 shows an overhead plan, cutaway view of an upper right corner of a PSIC 18, an LN 12, and the PTs associated therewith. FIG. 5 is explicit as to the location of several of the particular components, but partly diagrammatic, just showing the relations between components without concern for exact location. (Again, the parent application contains a more detailed description of the PSIC. In particular, it is critically important for purposes of making those inter-PSIC 18 joinders that both of the outward ends of the V_(dd), GND, and SPT 14 lines do in fact emerge slightly beyond the edge of the PSIC 18 itself. When seen in combination with FIGS. 6 and 11, the importance of that emergence to the circuit functioning will become clear. (It may be noted in passing that with respect to the independent operation of the LNs 12, that is made quite clear by the fact that none of the CPTs are included here in this grouping of elements that connect to another LN 12, while great care is being taken here to ensure that the Signal Lines (SLs) do indeed make that cross-LN 12 connection.)

PSIC 18 in FIG. 5 is 2-D and has a two layer structure, i.e., a circuit layer and above that a signal layer. The lower circuit layer is shown in darker print, and the upper signal layer is made to be of lighter print in order to emphasize the lower circuit layer. That lower circuit layer contains the LN 12, the CPTs, V_(dd), and GND, which are all marked, while (operationally) the upper layer contains the SPTs 14 and, most importantly, the SLs for each terminal of the LN 12, which SLs extend both horizontally and vertically (in the drawing). V_(dd) extends across near to the top of FIG. 5 and GND across near to the bottom of the drawing. Every LN 12 must have its own V_(dd) and GND connections nearby, since there indeed may be some encodings in which the specific LN 12 (and only that LN 12) would be involved in the circuit.

Four different flows of signal are shown, with three paths in each as shown by the small rightward- and upward-pointing arrows contained therein, which three paths are the “Drain Signal Line” (DSL) 28, the “Gate Signal Line” (GSL) 30, and the “Source Signal Line” (SSL) 32, labeled respectively as No. 1 (outgoing upward); clockwise to No. 2 (outgoing to the right); another clockwise, No. 3, (incoming upward); and finally a last clockwise, No. 4 (incoming rightward). Those lines are labeled in both the horizontal and vertical directions as “DSL 28,” “GSL 30,” and “SSL 32,” respectively. In addition, the letters “D,” “G,” and “S” are shown within small circles at or near the respective points of intersection of the horizontal and vertical SLs, at which points those two directions of the SLs are joined.

It is of course essential that the DSL 28, GSL 30, and SSL 32 lines should not come into contact with one another. Although not visible in FIG. 5, the means by which that is accomplished is through the use of “Pedestals” (PEDs) 26, which are electrically conductive, post-like structures that extend from points on the DR 20, GA 22, and SO 24 terminals in the lower level up to the respective DSL 28, GSL 30, and SSL 32 in the upper level. As to GSL 30 and SSL 32, it was possible to show PED 26 as contacting those SLs, as shown by respective “G” and “S” labels within circles, at the point of intersection of their horizontal and vertical parts, but with DSL 28 it was necessary to offset that PED 26 and the label “D” to a point along the line of the DR 20 terminal as it extends outward from the LN 12 body. As shown (partly) in FIG. 6 but invisible in FIG. 5, beneath (or nearly so) those encircled “D,” “G,” and “S” notations in FIG. 5 those PEDs 26 of differing heights have thus been placed to connect between the SLs 28-32 in the upper level and the respective DR 20, GA 22, and SO 24 terminals in the lower level. Both that placement of the SLs at different heights and the electronic connection between the two levels have thus been carried out. The DSL 28 is the highest, the GSL 30 the next highest, and the SSL 32 the lowest.

The LN 12 is shown just to the left of and slightly below the center of FIG. 5, and the three CPTs are shown in the lines that extend therefrom. Specifically, CPT1 is shown in the line between the LN 12 and V_(dd), CPT2 lies in a side extension from the GA terminal that goes on to connect to I/O 16, and CPT3 lies between LN 12 and GND on the SO 24 terminal. (In this context, “between” does not necessarily imply any direct connection, since other components may intervene. Similarly, the connections to the OT need not be taken literally.) Since just about any kind of energy transmitting device could be used as the “Operational Transistor” (OT) here, including junction transistors, bipolar transistors, MOS or CMOS, Pass Transistors, Optical (and indeed even water pipes!), etc., in order to preserve that broad scope it was elected not to limit the OTs to any specific device in FIG. 2 and thereafter, but simply to leave that issue undetermined and instead of showing specific circuitry within the circle representing the “Logic Node” (LN 12) or OT, it was left to the reader, as a person of ordinary skill in the art, to make those decisions. (What that energy transmitting device might be has no bearing on the principles of scalability and super-scalability.)

Besides the top-down method of contacting the PT terminals, the PSIC 18 has a second unusual feature, which is laying out the LNs 12 at an angle to the geometry of the array grid (see FIG. 5). This was done to minimize capacitive reactions of the upper SLs with the lower layer components, i.e., to allow the horizontal and vertical passage of the upper level SLs at locations that are not aligned throughout their full lengths with any of the components of the lower level, and particularly not to cross directly over the LN 12. Placing the LN 12 and the extension of its terminals at an angle of approximately 14 degrees (14°) out therefrom, as shown in the drawing, substantially eliminates much of that face-to-face relationship between the upper- and lower-level components.

In order to carry out the desired circuit structuring, it is necessary for each OT terminal to be able to connect to all of the terminals of neighboring OTs, both rightward and upward, and to receive that many inward connections as well. As already noted, an exception to that rule is that among all of the basic logic circuits, nowhere were there found either a GA 22 to SO 24 connection or an SO 24 to GA 22 connection, and it may be noticed that those connections are not shown in FIG. 2, FIG. 5, or FIG. 6.

The manner in which those connections are separated out, but yet converge into single DR 28, GA 30, and SO 32 SLs, is shown in FIG. 6, which shows those connections for the horizontal case. (The vertical case is essentially identical to the horizontal except for the order of the SPTs 14, so it was thought not to be necessary to show that version as well.) It can be seen that in this horizontal version, each of the DR 28, GA 30, and SO 32 SLs shown in FIG. 6 to the right of the SPTs 14, with the exception of the GA 30-SO 32 and SO 32-GA 30 connections noted above, have made connection to each of the DSL 28, GSL 30, or SSL 32 lines on the right-hand side of the SPTs 14, thus to leave only those three SLs to make connection to the next LN 12, while at the same time providing, as shown by the arrows marked “OLN” and “RLN” on the respective left and right sides of FIG. 6, for every (with the exception of the missing GA 22-SO 24 and SO 24-GA 22 lines) SL on the “Originating Logic Node” (OLN) to connect to every SL on the “Receiving Logic Node” (RLN). The lines shown in FIG. 6 (and FIGS. 2 and 5), which as noted above are essentially duplicated in the vertical direction except that the order of the SPTs is slightly different, thus make it possible to structure every kind of basic logic circuit as may be needed to carry out a full range of IP. The connections shown, in other words, suffice to carry out all of the 16 possible logic functions of Boolean logic, and on that basis, presumably any algorithm that could be written to execute any IP task that might arise in the real world.

For purposes of understanding the operation of these PSICs 18, especially as to the super-scalability, it is important to notice now why it is that the order of the SPTs differs between the horizontal and the vertical versions of the inter-LN 12 lines. As described earlier, the OT was set at an angle so as to permit the signal lines to avoid lying in parallel with any lower components any more than was necessary. That was of course not an entirely successful scheme, but nevertheless there was some minimization of those inter-level capacitive effects. (The sizes of those lines are of course much exaggerated for purposes of easier viewing in the drawing, so the capacitive effects will not in practice be as large as would seem from the drawing.) As it then turned out, that minimization was brought about by having the horizontal lines laid in the order G, D, and S, reading top to bottom, while the vertical lines had the order D, G, and S, reading left to right. It was only in that way that the SLs were able to be fitted past the IN_(j) and most of the terminal lines extending therefrom with a minimum of capacitive interaction. The significance of following those orders of arrangement exactly will be seen when it comes to joining one PSIC 18 to another.

In what now follows a number of standard gate circuits will be shown as having been structured by IL methods, together with the code by which the particular circuit was structured. Each such IL structure will be preceded by a drawing of the current equivalent of that IL circuit. An arbitrary placement of the circuits within a gross 10×10 PSIC 18 will be used to illustrate the use of both the LI_(i) and IN_(j) values as was noted above, followed by the rest of the code needed to enable the proper LNs 12, CPTs, SPTs 14, and the I/O 16, when used, to form the circuits being structured.

The LI_(i)s are the numbers of the LNs 12 as assigned in a left-to-right count and then downward through the rows in the same manner, and the IN_(j) are the binary versions of those LI_(i)s. The locations of the various circuits within the PSIC 18 will be selected arbitrarily, as will also be the destinations of those circuit outputs. The “iiiiiiiiii” IN_(j) value will use a 10-bit code, which of course must be consistent throughout all of the LNs 12 of an algorithm, and all bit sizes of data regardless of the size of any particular number, since otherwise one would not know where the IN code left off and the PT codes began. Only 2-D embodiments will be shown, but just for purposes of illustration the direction code will be of 2 bits so as to accommodate a third dimension.

Now in determining the overall design of an ILA so as to meet some range of IP tasks, these LI_(i) and IN_(j) values, as well as that process of determining those values, relate directly to the issues of scalability and super-scalability, since if a second PSIC 18 had had to be added to a first in order to have enough space for some algorithm, then those values for much of the resultant composite PSIC 18 will have to be re-determined, or otherwise neither of those features would be operable and could not be demonstrated. A rapid way of restructuring the values of all of the IN_(j) thus becomes quite pertinent.

As will be the case with all of the LN 12-structured circuits to be shown here, only those PTs that have been enabled so as to be a part of the circuit being structured are shown. Unless blocked from so doing, the LI_(i) will be shown to the right of and a bit above the “IN” circle for the LN 12, and the IN_(j) will be shown as the leading (most significant bit positions) bits of the full code, which will be located just below the GND symbol, or below the “IN” circle if no GND is shown. (If the indicated space is blocked, that full code will be placed elsewhere, but be very visible in any event, so there should be no difficulty in locating any of these code elements. In the latch circuit shown below, the codes for the top row of LNs 12 are placed above those LNs 12.)

This sequence of circuits will start with the simple “BYPASS gate” (BYP), since it is the most simple possible “circuit” (The BYP, like the inverter, is of course not a “gate” in any strict sense, but is termed one herein simply to have a consistent terminology.) and is quite ubiquitous, with a very useful function to be used in resolving a geometric problem brought about by the inflexible, orthogonal nature of the LN 12 array as seen in FIG. 3: a data bit may not be in the location where it needs to be in order to carry out some specific function, and the BYP will be used to move that bit to where it is needed, as will be seen in the XOR gate. (IL has no diagonal connections, but a version thereof that did have such connections could no doubt be devised.) The BYP is also used when widely separated parts of a composite circuit need to be brought together (or in an obvious example, in gathering up the partial sums in an addition and like operations). As a part of that process, pairs of inverters may also have to be interspersed in a sequence of BYPS so as to avoid having the signal deteriorate too much in strength if only BYPs were to be used. This first “circuit” will be unique to IL (at least in the role of what purports to be a circuit), since it really is just the equivalent of a wire connection from one place to another.

The latch (memory node) will be shown to illustrate that IL serves also to carry out sequential logic. That memory capability could be important in the event that an algorithm was to bring about any instances of data dependence. From this central core of circuits there would seem to be no algorithm for which a binary logic solution could not be developed that would accommodate the IL methodology. Finally, an XOR gate will be shown in such manner as to illustrate both scalability and super-scalability.

Thus, FIG. 7 a (sheet 7) shows a standard wire, followed in FIG. 7 b 1 (sheet 7) by the corresponding horizontal BYP. For the purpose of completion, FIG. 7 b 2 (sheet 7) then shows a vertical BYB. The horizontal case is seen to connect through SPT 5 to the GA 22 terminal of the next adjacent LN 12; what the destination location may be has nothing to do with the existence of a BYP gate, since it is only necessary in forming a BYP gate that the signal arrive and leave the BYP LN 12 along the same terminal. The vertical BYP “gate” connects through SPT 11 to the DR 22 terminal of the next upward LN 12. The BYP is also unique in having no voltage applied to the LN 12 thereof which, of course, is not then even operating, since all that is required to have a BYP is to have enabled the SPT 14 that is on the same outward (No. 2 or 1) terminal line as that which had brought in the signal (No. 4 or 3), thus to pass the signal on to the next LN 12.

Again as to the BYP gate specifically, in the horizontal version of FIG. 7 b 1 (sheet 7) the full code “iiiiiiicccs₁s₁dds₂s₂=0010111000010110,” the first seven bits “iiiiiii”=0010111, which is the IN_(j) for the LN 12 of that BYP, the binary form of the arbitrarily selected LI_(i)=23. In a 10×10 PSIC 18, that would be the third rightward LN 12 in the third row. The next three bits are the CPT codes, with the “000” codes showing that none of the CPTs were to be enabled. In the remaining six bits, constituting the code for the single SPT 14 to be enabled, the first “01” means that the proximal end of the SPT 14 connects to the DR 20 terminal of the OLN, the next “01” indicates that the SPT 14 is to extend rightwardly, and that final “10” means that the distal end of the SPT 14 happens to connect to the GA 22 terminal of the RLN.

In FIG. 7 b 2 (sheet 7), which shows the BYP extending vertically, for which the full code is “0110100000011001, the INj was arbitrarily selected to be 52, i.e., the second LN 12 over in the fifth row, for which “iiiiiii”=IN_(j)=“0110100.” The code right after the “s₁s₁” code differs from that of the horizontal version in that while the originating terminal is the same (“01” for the DR terminal), the 13^(th) and 14^(th) bits that form the direction code dd are “10” instead of “01,” thus to indicate that structuring will proceed in the vertical direction rather than the horizontal, and the last two bits are “01” instead of “10,” indicating that connection at the RLN is made to the DR 20 terminal rather than the GA 22 terminal. As shown in FIG. 2, the “11” SPT 14 is that which extends from a lower DR 20 terminal to an upper DR 20 terminal as is seen in FIG. 7 b 2.

The next IL-structured circuit, a BRANCH gate, of which a conventional version is shown in FIG. 8 a, in IL drawn as a combination of an inverter and a BYPASS gate as inherent parts of its structure. As the name suggests, this circuit simply takes a single input and branches that signal out into two bits, then to enter into two different LNs 12. The LN 12 that does the branching, as shown in FIG. 8 b (Sheet 7), is the 92 LN 12, meaning the second LN 12 in the ninth row. This is the first instance in these examples in which an LN 12 has two SPTs 14 to be enabled, which are the 5 SPT 14 from the DR 20 terminal (01) of the 92 LN 12 (among the “2” outward pathways) and extending rightward (01) to the GA 22 (10) terminal of the RLN; and then the 11 SPT 14 on that same DR 20 terminal of the 92 LN 12 and extending upward (10) (among the “1” outward pathways) to the DR 20 terminal (01) of the 82 LN 12. Both outputs are inverted, but then with the 82 LN 12 serving as a BYPASS gate and those two outputs being the same, they will be out of phase by one cycle, since the 82 LN 12 output required two LN 12 operations to be formed, but the 92 LN 12 required only one.

Starting at the BYP gate at the top and proceeding downward through the PSIC 18, the full code for the 82 LN 12 is generated as being 1010010 for the IN_(j), followed by three “0's for the “ccc” code, a “01” to indicate that the proximal end of the 5 SPT 14 connects to the DR 20 terminal of the 82 LN 12, another “01” to indicate that the 5 SPT 14 extends to the right, and then a “10” to show that the distal end of the 5 SPT 14 connects to the GA 22 terminal of the RLN, whatever it may be. The full code for the 82 LN 12 is thus 1010010000010110, for a total of 16 bits.

The lower LN 12 in FIG. 8 b, which in a 10×10 array must have an LI_(i) of 92, which is 10 more than that of the LN 12 that it is directly below, has =1011100, then the ccc=101 for enabling the “1” and “3” CPTs, and then the signal code, which for the horizontal 5 SPT 14 is “01” for the DR 20 origin of the proximal end, “01” for extending rightward, and then “10” for the distal end of the SPT 14 on the GA 22 terminal of the RLN. The second SPT 14 code must then be added, which for the 11 SPT 11 is again 01 for originating on the DR 20 terminal, 10 for proceeding upward, and then 01 for the distal end of the SPT 14 connecting to the DR 20 terminal of the 82 LN 12.

The complete code comes out as 1011100101010110011001 of 22 bits for the BRANCH gate as a whole, and is made by concatenating that for the 92 LN 12 onto the right side of that for the 82 LN 12, reading downward through the PSIC 18. In operation, that code forms a CL, but would also have to include the codes for any other LNs 12 that participated in that same step of that same algorithm. (It does not matter in what order the two SPTs 14 are entered, but of course the six bits that make up a signal code must be entered intact, without mixing any of the code between the two SPTs 14. When there are two SPT 14 codes to be entered, this applicant has made the habit of entering the horizontal code first, and then the vertical. It should be recognized that there can be no more than one SPT 14 connecting out to a particular LN 12, so if there are two codes to be entered, it is evident that one must go out horizontally and the other vertically, so as to go to two different LNs 12.)

The SPTs 14 that are enabled are shown in the BYPASS and BRANCH gates of FIGS. 7 b 1, 7 b 2, 8 b (all Sheet 7), and will be hereinafter, simply as small boxes with a “1” therein to indicate that a “1” enabling bit has been applied to the gate terminal of the SPT 14 that is represented by that box, indicated by a numbered line attached thereto. There is also an adjacent letter “d,” “g,” or “s,” to identify the “target” terminal on the RLN.

The first “real” circuit to be shown here, meaning that a bit is actually to be operated upon rather than just being moved, is the NOT gate, or inverter, which consists of a single LN 12 having an input at the GA 22 terminal thereof and then an output of opposite sense at the DR 20 terminal. Following the conventional inverter shown in FIG. 9 a (sheet 8), the next drawing shows the IL version thereof in FIG. 9 b (sheet 8). The full vector code for the IL inverter is 0010010101010110, wherein the IN_(j)=“0010010” is for an LI_(i) of 18, as was arbitrarily selected. Of the three CPTs having the “ccc” code, the 1 and 3 CPTs are enabled, so the “ccc” code is “101.” Then finally, in the “ssssss” code, the output is taken from the DR 20 terminal (01) of the OLN, goes to the right (01), and connects to the GA 22 terminal (10) of the RLN. That output connection to the GA 22 terminal of the RLN is of course only an example, since any output taken from that DR 20 terminal of that LN 12 would qualify that LN 12 as being an inverter.

The next circuit is a 2-bit AND gate, the conventional version of which is shown in FIG. 10 a (sheet 8), followed by the IL version in FIG. 10 b (sheet 8), which is the first one here (other than the BRANCH gate) to have more than one LN 12. The top LN 12 has the arbitrarily assigned LI_(i) of 66, and thus an IN_(j) of 1000010. The “ccc” code is 100, indicating that only V_(dd) is connected, with the following SPT 14 code being a first “01” to indicate a DR 20 connection of the 5 SPT 14, then another “01” to indicate a rightward direction, and finally a “10” to indicate that the distal end of that 5 SPT 14 connects to the GA 22 terminal of the RLN. The full code for the 66 LN 12 is thus 1000010100010110 of 16 bits.

The connection between the two LNs 12 is made by an SPT 14 located on the lower LN 12, which has an LI_(i) of 76 (again 10 higher than the LN 12 above) and the IN_(j) code of 1001100. The following “ccc” code is “011,” indicating that CPT2 is enabled along with the connection through CPT3 to GND. The signal code has the 13 SPT 14 connected at the proximal end to the DR 20 terminal by a 01 code, then a 10 to indicate the vertical structuring, and then finally a 11 code to accomplish the connection to the SO 24 terminal of the RLN. (It should be understood that these code entries do not merely show the operator what connections are being made, e.g., selection of the 13 SPT 14 physically requires the enabling of that SPT 14, from which the operator is able to see that the SPT 14 in use connects upwardly from the DR 20 terminal; e.g., it would not be possible to select the 13 SPT 14 and then select a 01 code to indicate a horizontal structuring, since it is that 10 for upward structuring that selects the 13 SPT 14 (or the 11 or 12, depending upon which RLN terminal was being selected to be the terminus of the connection.) This is the first IL circuit herein to show an external signal input, which connects to the I/O 16 terminal.

The full code for the 76 LN 12 is shown beneath that for the 66 LN 12, and turns out to be 1001100011011011, again of a 16 bit length. That length was suggested above to be used to show where the code for a first LN 12 has been completed and the second was ready to start. That might be useful for the operator in “proofreading” the code entries, but it is not necessary for operational purposes: with a fixed IN_(j) code length of 7 bits the LN 12 code length will be fixed at 16 bits if one SPT 14 is enabled, 22 if two SPTs 14 are enabled on the same LN 12 (there could be no more than two directions from the LN 12), or 32 if, as in this AND gate, two LNs 12 are fully encoded. (In theory, with two LNs 12 and two SPTs on each the CL would be 44 bits long.)

An OR gate is shown next, the conventional version thereof being shown in FIG. 11 a (sheet 9) and the IL version in FIG. 11 b (sheet 9). The latter IL version has LI_(i)=88 for the first LN 12 and 89, as a “next nearest (rightward) neighbor” for the second. For that leftward 88 LN 12 the IN_(j) is 1011000, with the “ccc” code=101, and the SPT 14 being “01” for a proximal end of the SPT 14 connection to the DR 20 terminal, another “01” for a rightward extension, and then another “01” code for the distal end of the SPT 14, which connects onto the DR 20 terminal of the RLN, i.e., the LI_(i)=89 LN 12. In view of that last connection, the “ccc” code for the LI_(i)=88 LN can be “001” instead of “101,” since that LI_(i)=88 LN 12 can take its voltage through the SPT 14 that extends from the DR 20 terminal thereof over to the same terminal on the 89 LN 12, that connects to V_(dd), thus to provide the required V_(dd) power for this LI_(i)=88 LN 12. As it stands, however, the full code for the 88 LN 12 is thus 1011000101010101.

The full code for the rightward LN 12 practically writes itself and is 1011001101010110, which comes from IN_(j)=1011001, “ccc”=“101,” showing that in the “ccc” code connections are made to V_(dd) and to GND, and then the signal code is “01” for the proximal end of the SPT 14 being on the DR 20 terminal of the 89 LN 12, a “01” for the rightward direction of the signal, and finally a “10” for the distal end connection to the GA 22 terminal of the RLN. The input to the rightward LN 12 must evidently be coming in from below that LI_(i)=89 LN 12 as shown by the dashed arrow line (i.e., from the 99 LN 12), since the CPT2 on that 89 LN 12 is not enabled for an external input through I/O 16, and the only other source for such signal, which is the leftward 88 LN 12, is already acting as the other input to the 2-bit OR gate. (The notation “Data In/Out” and the two arrows in FIG. 11 b are meant to suggest that with CPT2 enabled, the data to be operated upon could indeed come in from outside of the PSIC 18, rather than from the 99 LN 12.).

The NAND gate will of course simply be an AND gate followed by an inverter, and the same as to an OR gate to form a NOR gate, so it was not deemed necessary to show those circuits in detail, especially since the next “gate” shown, which is a memory latch, will contain two NAND gates. The simple SR (“Set-Reset”) flip-flop will be used as an example of a sequential circuit, so an iconic version of the conventional NAND-based SR flip-flop is shown in FIG. 12 a (Sheet 9). (The matter of being “NAND-based” is mentioned because an equivalent latch can be structured using NOR gates.)

This next IL circuit, the SR flip-flop, presents some interesting opportunities in the means by which the circuit is structured. In the first place, it has been the standard practice in treating this latch to show the two NAND gates as being side-by-side, and as shown in the iconic drawing in FIG. 12 a, pointing in the same direction, and as a result having the two outputs of the NAND gates crossing each other in the center of the drawing. In the IL structuring, the lower NAND gate has been reversed in direction, thereby to avoid the need to have crossed wires in the connections from the output of one NAND gate to one of the inputs to the other NAND gate.

Another consequence of the latch circuitry is that the reversed NAND gate used here requires the circuit structuring to proceed in a direction opposite to that of the signal flow, which of course, with pass transistors being bidirectional, is a perfectly legitimate procedure. In FIG. 12 b (sheet 10), the upper NAND gate is structured in the usual left-to-right manner, and the signal flow is in the same direction. In the lower NAND gate, the structuring is also from left-to-right, but given that the connections are restricted to going upward and rightward from the OLN, the signal flow is downward, leftward, and then upward again, opposite to the usual manner of structuring circuits. Of course, that makes not the slightest difference in the operation of the latch, since it is immaterial to the operation of the SPTs 14 in which direction the signal may be flowing.

Returning now to the RS flip-flop of FIG. 12 b (Sheet 10) specifically, the LNs 12 are numbered 44, 45, and 46 for the upper NAND gate, and 54, 55, and 56 for the lower NAND gate. The “S” (set) and “R” (reset) locations are marked at the I/Os 16 of the “top” (closest to V₁) LN 12 in each of the NAND gates, with “S” connecting to the top LN 12 (45) and “R” to the bottom one (55). “Q” and “Q-bar” appear at the respective outputs of the NAND gates, with “Q” deriving from the top NAND gate, which is associated with the “S” terminal, and “Q-bar” with the bottom “R” NAND gate.

For access to these quantities, S and R are already on I/O 16 outputs, while Q and Q-bar, having both appeared on a DR 20 terminal at a corner of the circuit, could easily be passed on to a GA 22 terminal of an adjacent LN 12 and then through CPT2 to an I/O 16 site (e.g., through the 5 SPT 14 of the 46 LN 12 to the GA 22 terminal of the 47 LN 12 and then the CPT2 of the 47 LN 12 to connect that “Q” site to the I/O 16 site, and then the 7 SPT 14 of the 53 LN 12 from the GA 22 terminal thereof to the DR 20 terminal of the 54 LN 12, which is the “Q-bar” position. CPT2 of the 53 LN 12 would then en connect that point to I/O 16.).

The detailed description of the RS flip-flop can begin with the 44 LN 12, as the top left LN 12 in FIG. 12 b, which has the full code 0101100001010111, as shown above the LN 12 rather than below for reasons of space in the drawing. For reasons of space, the CLs of the LNs 12 in this top row will all be found above the LN 12, and for the 44 LN 12 that full CL code is made up of IN_(j)=0101100, “ccc”=“001,” meaning that only the CPT3 to GND is enabled; then a “01” for the proximal end of the SPT 14 connecting to the DR 20 terminal, another “01” for the SPT 14 extending to the right, and “11” for the distal end of the SPT 14 connecting to the SO 24 terminal of the RLN, by way of the 6 SPT 14.

That signal is passed on to the SO 24 terminal of the 45 LN 12, for which LN_(j)=0101101; the “ccc” code is 110, meaning that both CPT1 and CPT2 are enabled, the SPT 14 code is first a 01 for the proximal end of the SPT 14 being on the DR 20 terminal of the 45 LN 12, then another 01 for going rightward, and then a 10 for the distal end of the SPT 14 connecting to the GA 22 terminal of the RLN after passing through the 5 SPT 14, that RLN being the 46 LN 12. Thus, while the 44 LN 12 had the GND but not the V_(dd) CPT enabled, being the “bottom” LN 12 of the AND gate, the 45 LN 12 has the V_(dd) but not the GND CPT enabled, as being the “top” LN 12 in the AND gate, the two LNs 12 then being connected in series.

In order to complete the structuring of a NAND gate, that AND gate output must pass through an inverter, which must be the 46 LN 12. Since that LN 12 receives the signal from the 45 LN 12 at its GA 22 terminal, to provide the inverter the 46 LN 12 needs only pass that signal on from its DR 20 terminal, as it indeed then does. For that 46 LN 12. the IN_(j)=0101110, ccc=101 for enabling V_(dd) and GND, and then there is no SPT 14 code, or rather the SPT 14 code is 000000 since connection to that DR 20 must be made from the LN 12 that is below that 46 LN 12, i.e., from the 56 LN 12. The full code then becomes 0101110101000000. This will be the start of a series of reverse coding, in which the SPT 14 to be used is one on the RLN, that then reaches back to the OLN. That connection in this case is through the 14 SPT 14 of the 56 LN 12.

The 56 LN 12 code begins with IN_(j)=0111000, followed by ccc=001 to indicate that only the CPT3 to GND is enabled; a 10 code for the SPT 14 that has the proximal end thereof on the GA 22 terminal of that LN 12; then another 10 code indicating that the SPT 14 extends upward, and finally a 01 code for connecting the distal end of the SPT 14 onto the DR 20 terminal of the 56 LN 12. That leads to a full code of 0111000001101001. That connection is the first one of two that connects the output of one NAND gate, in this case from the 46 LN 12 to an input of the other, i.e., the 56 LN 12.

Again going leftward, connection must first be made from the 56 LN 12 back up to the 46 LN 12, which is accomplished by the 14 SPT 14, of which the proximal end connects to the GA 22 terminal of the 56 LN 12 and then extends upward to the DR 20 terminal of the 46 LN 12, thus to form the 46 LN 12 into the inverter that converts the 44-45 AND gate into a NAND gate. Now as to the 56 LN 12 itself, the INj thereof is 0111000, the ccc code is 001, to indicate that only the CPT3 to GND is connected, and then as noted above, the GA22 connection is produced by a 10 code, the upward connection by another 10 code, and the connection to the DR 20 of the 46 LN 12 by a 01 code. The full code of the 56 LN 12 is thus 0111000001101001.

Connection must then be made from the SO 24 terminal of the upper (of the AND gate) 55 LN back to the DR 20 terminal of the lower 56 LN 12 of the AND gate, which would be through the 16 SPT 14 of the 55 LN 12. The arrowheads on the signal line point downward from the 46 to the 56 LN 12, and then leftward from the 56 to the 55 LN 12, and similarly thereafter to the 54 LN 12. The full code of the 55 LN 12 is 0110111110110101, consisting of an IN_(j) code of 0110111, ccc=110 to show that CPT1 and CPT2 were enabled, and then 11 for a connection of the proximal end of the SPT 14 to the SO 24 terminal of the 55 LN 12, a 01 code to show that the SPT 14 extends to the right, and then a 01 to reflect the connection of the distal end of the SPT 14 to the DR 20 terminal of the 56 LN 12.**

The 56 and 55 LNs 12 constitute the AND gate, with the 55 LN 12 being the higher of the two (closest to V_(dd)), and then the 54 LN 12 as an inverter will convert that AND gate into a NAND gate. That means a connection through the 7 SPT 14 from the GA 22 terminal of the 54 LN 12 back to the DR 20 terminal of the 55 LN 12. The location of the 54 LN 12 is given by IN_(j)=0110110, and then ccc=101 to show the enabling of CPT1 and CPT3, and then for the 7 SPT 14 code a 10 for the proximal end of the SPT on the GA 22 terminal of the 54 LN 12, a 01 for the rightward direction of the 7 SPT 14, and then another 01 for the connection of the distal end of that 7 SPT 14 to the DR 20 terminal of the 55 LN 12. A second SPT 14 is enabled for the connection of the output of this second NAND gate to an input of the first NAND gate, which is the 12 SPT 14 of the 54 LN 12 connecting at the proximal end thereof to the DR 20 terminal of the 54 LN 12, shown by a 01 code, then a 10 showing the upward direction of the 12 SPT 14, then a 10 to show the connection of the distal end of that 12 SPT 14 to the GA 22 terminal of the 44 LN 12, thus to complete the encoding of this SR flip-flop. As indicated, this lower NAND gate is structured going in the opposite direction to that of the upper NAND gate so as to avoid needing to cross the two output-input connections. This RS flip-flop latch is probably unique in the wide variety of IL encoding practices in being made of so many so many different parts in such a small circuit. (Except possibly for aesthetic reasons, it is not clear why this latch is usually drawn with the two NAND gates being “pointed” in the same direction. In fact, having those gates going in opposite directions and without the crossed wires as done here would be more suggestive of how the device operates, in showing the paired output-to-input relationship more clearly.)

Operations

One important aspect of IL is its presumed low use of power. In current electronics practice, turning on an instrument essentially involves turning on everything. In IL, by contrast, until an algorithm begins to be executed, at any given time only those transistors that are involved in the one step of the algorithm then being executed will be receiving any power. (Of course, there will be power to the monitor and various peripherals in both cases.) It is as though the algorithm was being executed using only the power of enough LNs 12 to structure the circuitry of a single step. That kind of energy economy should be a boon in those markets that depend upon battery-operated devices such as cell phones, remotes, laptops, etc.

At the high end of the energy consumption scale, there are some circumstances in which the maximum use of as many LNs 12 as possible would be sought, as in the maintenance and interpretation of the Gross National Product data base, the conduct of the census, the IRS files, the FBI files, the Department of Defense, Home Security, the Patent and Trademark Office data bases, the content of the National Archives, etc., or on the scientific side the data pouring out of the Hubble telescope, the data bases of the Center for Disease Control, the Department of Health, or the data pouring out of the Large Hadron Collider at a rate of 15 petabytes per year, etc. There being no limit to the upper size or numbers of the PSICs 18 making up the system for treating any of those or similar massive data handling tasks except for the practical factors of space, time, and money, and with a lower limit of one LN 12, there seems to be no data handling problem now existent that could not be handled by IL.

The small grained character of IL also allows for smaller embodiments thereof, so that where appropriate IL could replace ASICs in many of the embedded types of usage. An advantage as to the personal computer is that it would no longer be necessary to await the loading in of some huge program in order to begin some desired operation—to start an algorithm in IL requires only the encoding of a first small set of the operational elements that will constitute the first step of the algorithm, and indeed as the first cycle of the operation, with the following operational elements being encoded “Just In Time” to execute each next step of the algorithm whence the name “Instant Logic.” (Actually, provided the PS 10 were large enough, nothing would prevent loading all of the CLs of the algorithm at once, but it would be wasteful of energy to do so.) It would seem possible to apply IL to the full range of consumer products, it would also seem that there would be no task now carried out using microprocessors and FPGAs, etc., that could not be carried out using IL. It would only be questionable whether the adoption of IL would be worthwhile as to the many tasks now carried out by the variety of small ASICs now in use. (There is also the question of whether the prospective greater speed of IL procedures is actually needed in many of the ASIC applications—probably so in motor vehicles and elevators, but perhaps not in a washing machine.) Even so, IL may be chosen not for speed gains but for purposes of conserving energy and ease of maintenance.)

On that matter of maintenance, that should be quite an easy task: control of the IL operations would not be spread out through the system, but would generally be local, and if a fault in some step of the process was identified, it is just a matter of replacing the module in which the step takes place as a permanent fix, or on a temporary basis the step operations could easily be sent through a different set of LNs 12, thus to bypass whatever LNs 12 that were not properly functioning, as a matter of re-writing the code (i.e., the relevant code lines).

In conceptual terms, the ILA is quite simple, but in practical terms, it is quite complex, requiring creative encoding in order to get the various algorithms, and steps of algorithms, functioning in a coherent manner, without “collisions” where two or more algorithm steps were vying for the same LN 12. Of course, one simply steers the paths of circuit encoding away from each other, but if there is not sufficient space to do so, the paths of other algorithms might also need to be re-directed, so the process could get complicated. Thus, although the avoidance of collisions is conceptually a simple matter, actually to succeed in doing so could get complicated. The development of Code Modules that do not collide internally, but are yet compact so as not to have “hoarded” too much PS 10 space, is a labor-intensive task.

Of course, cost would remain an issue in any of those contexts, given the complexity of the PSIC 18 and the means for entering code and data into the PSIC 18. However, that IC is substantially less complex than many that can be seen in the literature. Indeed, the highly repetitive nature of the PS circuit augers well for mass production methods, and the simplicity of the IL equivalent of programming would seem to offset any extra cost of the IL PSIC 18, even if there is such an extra cost, which seems doubtful. The “encoders” (those persons who would encode the IL algorithms) would need to wipe from their minds all thoughts of C++, PASCAL, instructions, CPUs, ALUs, networks, loops (but not conditional transfers), pointers, dlls, etc., and think only in terms of what binary gates would be needed to carry out each next step of whatever the algorithm might be. A code module developed for “performance” computers might still be easily transferred to an ASIC context, run through procedures such as that set out in FIG. 4 (sheet 4), and then just copied into the ASIC.

For that purpose, various code modules that would structure such more complex circuits as ADD, SUBTRACT, MULTIPLY, AND DIVIDE circuits (all of which would require extensive routing of partials sums, etc., to gather the bits together), SORT, SEARCH and SEQUENCE circuits, and circuits for a wide range of mathematical operations, such as MATRIX INVERSION, FFTs, BESSEL FUNCTIONS, MATHIEU FUNCTIONS, hyperbolic cosines, etc., could be prepared in advance, the use of which would only need to be specialized to the particular algorithm by the need to identify the IN_(j) values of the LNs 12 from which the data to be processed would be acquired, and as described above, the code module (CM) would then identify the IN_(j) values for all of the other LNs 12 that would be used in the algorithm.

Like the capability of executing complex algorithms, the data handling capability of IL is also essentially unlimited, as would be the scope of those SORT, SEARCH and SEQUENCE operations, which means that the data handling requirements of such institutions as the FBI or the USPTO, or even more challenging would be the highly data-dense undertakings such as the Large Hadron Collider, or as to relatively fixed data, indeed the entirety of both the scientific and other types of literature throughout the entire history of mankind, could be stored in a readily searchable and accessible manner, thus to have helped accommodate the “Information Explosion.”

Any projection of all of the tasks to which IL could be applied would be a very questionable enterprise, but the isotropic, continuous array-like construction of the area in which the actual IP takes place suggests even very complicated tasks for which the advantages of IL would very likely be substantial. One such task that is both obvious and in great need for improvement is that of image processing, in which the ability of IL to carry out large numbers of repetitions of some simple task at a very rapid rate would no doubt stand out.

The isotropic, continuous array-like construction of the area in which the actual IP takes place suggests that even very complicated tasks for which the advantages of IL would very likely be substantial. One such task that is both obvious and in great need for improvement is that of image processing, in which the ability of IL to carry out large numbers of repetitions of some simple task at a very rapid rate would no doubt stand out.

Another such application would be that of Artificial Intelligence, for which one can see two different advantages. As to the first of these, the essentially unlimited size of the PS would provide an equally unlimited data-handling capacity, thus to permit identification of relationships between even the most distantly related concepts. (The parent application sets out a data-sorting process (using conventional electronics) in which the depth of the variables addressed (i.e., of the sub-, sub- sub-, etc. variety) can be increased without limit.)

Another advantage of that array-like construction relates to the efforts being carried out in the Artificial Intelligence community to mimic the structure of the brain. As understood by this author, current thought in Artificial Intelligence is that for the most part, even though certain regions of the brain have been identified as carrying out particular tasks (sight, language, etc.), the more abstract mental processes seem to take place by way of synapses that are highly distributed, taking place at locations that are spread out through large areas of the brain. It would seem that presently, the Processing Space of IL could provide the kind of tabula rasa or “blank slate” on which models of that kind of brain function could be examined (which is not, of course, to say that the brain acts on the whole as a tabula rasa, which it most assuredly does not). The brain has an irregular array of cells that have multiple connections to other such cells, while the IL array has a regular array of cells that have multiple connections to other such cells.

Scalability and Super-Scalability

Turning now specifically to the matter of scalability and super-scalability, this first requires a view of another aspect of the PSIC 18, which is the all-important connection of the internal workings of a PS 10 with the outside world, of which for that purpose a portion thereof is shown in FIG. 13 (Sheet 11), specifically an upper right corner of a PSIC 18 chip as cut out from a wafer along the Cut Lines (CuLs), but also being cut along the Cutaway (Cut) lines in order to remove the portion shown from the rest of the PS 10. The PS 10 as a whole will contain some number of LNs 12 and associated PTs, all to form a single integrated circuit. The top of the PS 10 shows the Top Entry Apertures (TEAs) 58 for the Contact Pins (ConPs) 60, that as shown in the lower left hand corner of FIG. 13, will enter their own Contact Apertures (CAs) 56 within the conductive PEDs 26 shown in FIG. 6 (sheet 6) to bring in to the PSIC 18 the code bits for the gates of the CPTs and SPTs 14, to which the bottoms of the PEDs are connected, and one line will also serve the I/O 16. The number of LNs 12 and associated PTs that are contained within a single IC is evidenced by the number of TEA 58 groups that are visible at the top of the IC. The ConPs 60 have Conductive Wires (CWs 64) attached to the tops thereof that bring in that code and data from a central control circuit (not shown), this in fact being the “real world” connection. (These can be seen more clearly in the parent application, along with more detail as to the other components just set out.)

The forward face of the CuL shows the DSL 28, GSL 30, and SSL 32, as well as the V_(dd) and GND connections, and the TEAs 58 at the top for all SPT 14 connections for one full PE, and then the DSL 28, GSL 30, V_(dd), and three TEAs 58 as a partial representation for a second LN 12. As noted earlier, all of these that appear on the front surface of the integrated circuit chip are caused to protrude a slight bit from the body of the PSIC 18, which is required for the joining of one PSIC 18 to another. The top of the chip is used for connections from the encoding circuitry to the PTs to which code must be sent, and thus constitutes an “Operations” surface of the chip, while the facing front surface of the chip, as seen in FIG. 13 (sheet 11), constitutes the “expansion” surface of the chip, since that is where additional PSICs 18 are brought into a single or already composite PSIC 18, to add further PSIC 18 chips and thus expand the throughput of the ILA then in operation. The side of the PSIC 18 that lies along the rear thereof as indicated by the curved arrow includes the same set of outward extending connections DSL 28, GSL 30, and SSL 32, (not including V_(dd) or GND lines) for what in FIGS. 5,15 would be prospective “upward” connections.

The far side of the PSIC 18 contains an effective “mirror image” of the connections shown in FIG. 13, with the lines on that side also slightly protruding, so that by bringing another PSIC 18 up against the facing forward surface of the PSIC 18 shown in FIG. 13, all of the lines protruding from this front surface of the PSIC 18 will be found to be in alignment with those input lines (lines 4) on the back surface of that new PSIC 18, and electrical continuity will have been achieved through both PSICs 18. It is through those lines that the “limitation” on the scalability of IL noted earlier, that arises from the fact that only so many LNs 12 can be fit on a PSIC 18, is eliminated, since more PSICs 18 can be added at will. The XOR gate will now be described to show how those same connections give rise to super-scalability.

An XOR Gate

A conventional iconic form of the XOR gate is shown in FIG. 14 (Sheet 11), and an IL version of that same gate layout in FIG. 15 (Sheet 12), with the A, B, E, and G LNs 12 (as labeled below and to the left of the LN 12) being in the second row of the PSIC 18. (The LNs 12 were given a letter sequence in the order of how they came up for discussion, which is not necessarily the same as the order of their appearance in the circuit.) The structuring of the XOR gate had been initiated in the second and third rows of a 20×20 PSIC 18, but as it turned out, because of earlier circuit structuring, there was not space enough on that original PSIC 18 (PS1) for that XOR gate, so it became necessary to add another PSIC 18 (PS2), and these are both shown in FIG. 15, and are so marked by arrows at the upper right of the drawing.

With an x-axis width on PS1 of 20 LNs 12, an LN 12 that was in the second row and in the 18^(th) rightward position would have an LI_(i) of 38 in that original circumstance, which value is shown in FIG. 15, in parentheses just above the GA 22 terminal on the right. The respective values of 39 and 40 for the next two LNs 12 to the right are also shown. No further rightward value can be shown because without the addition of PS2 there is no rightward LN 12. With the known X_(M) value of 20, the LI_(i) values for the LNs 12 in the third row can be written in just as easily, i.e., as 58, 59, and 60, which are each 20 higher than the LN 12 immediately above each of them. With the addition of PS2 (also 20×20), however, X_(M) would have become 40, and the LI_(i) of that LN 12 would have to be 20 higher than that of the original, i.e., 58, and that value is shown in brackets just above the original value, if any. That value of 58 would have been achieved by traversing one full row and then 18 positions in the second row, followed in this case by the values 59, 60, and 61 with that 61 value now being an LN 12 available in PS2, these values also being shown in brackets above the original values.

With regard to the third row (the second row of the XOR gate), in the original situation, with no PS2 present, the LI_(i) values of the C, D, and F would have been X_(M)=20 higher than the values of the LN 12 just above each of those LNs 12, i.e., 58, 59, and 60, respectively, as shown in parentheses again just above and to the right of the LN 12, but again with no value being shown on the H LN 12 since not yet present, but then with the addition of PS2 those values would be based upon X_(M)=40 and the higher values of the A, B, E and G values, or 58+40=98 for the C LN 12, then followed by 99, 100, and 101, respectively, for the respective D, F, and H LNs 12, also shown in brackets above the earlier values, if any.

Rather than having to having to pick one's way through these LNs 12, however, it is seen that a pattern seems to have begun to emerge. That is, the LI_(i) values of a lower row are the same as the values of the row above with PS2 added, e.g., the LI_(i)=60 of the F LN 12 without the PS2 is the same as the 60 value of the E LN 12 one row above with PS2. Of course, that is as it should be, since either adding a 20×20 PS2 or moving down a row would each add 20 to the LI_(i). It then seems possible to enter LI_(i) values by simple inspection of the circuit drawing.

That having been done, it remains only to enter the corresponding IN_(j) codes into FIG. 15, and these are as follows, again shown slightly above and to the left of CPT1 (when space permits; otherwise to the right) and keyed to the letter designation of the LN 12. The 20×20 codes will be shown here first in FIG. 12 in parentheses, and then above those codes the 40×20 version in brackets. These codes are: 38 A IN_(j)=0100110; 39 B IN_(j)=0100111; 40 E IN_(j)=0101000; and G IN_(j)=0101001 (although in the 20×20 embodiment there is no G IN_(j) in the top row of the XOR gate, that code is shown, but then lined out, both here and in FIG. 15); for the bottom row: 58 C IN_(j)=0111010; 59 D IN_(j)=0111011; 60 F IN_(j)=0111100; and H IN_(j)=0111101 (although likewise in this bottom row there is no H IN_(j) in this 20×20 embodiment, that code is also shown but then lined out both here and in FIG. 15). As to the 40×20 embodiment, with the LI_(i) and IN_(j) codes both being shown between brackets, and disposed just above the corresponding 20×20 codes, for the top row these are as follows: 58 A IN_(j)=011110; 59 B IN_(j)=0111011; 60 E IN_(j)=0111100; and 61 G IN_(j)=0111101, and for the bottom row, 98 C IN_(j)=1100010; 99 D IN_(j)=1100011; 100 F IN_(j)=1100100, and 101 G IN_(j)=1100101.

One thing that can be noticed immediately is that adding to the size of the PSIC 18 has no effect on the circuit or signal codes, as shown just below the IN_(j) codes in FIG. 15, and remain unchanged as between the two embodiments. The formulae by which the IN_(j) can be calculated as were described with reference to FIG. 4 are shown just below the GA 22 terminals. The circuitry of FIG. 4 may be regarded by many as being superfluous if a drawing of the circuit sought to be structured were available, since in that case the proper codes to be used are essentially available by inspection of the circuit: it is no great task to realize, again, that that motion is relative, and that moving a circuit and modifying the counting system in use as by adding another PSIC 18 follow the same rules, in that, e.g., the numbers for the first half of the second row of the composite PSIC 18 will be the same as had been those numbers in the third row in the original case; the first half of the third row of the composite have the same numbers as had the fifth row of the original, etc., changing by the factor 2X_(M), To get the binary code for the right half of the composite will have the same relationship with the even-numbered rows of the original PSIC 18, and one can copy and paste from one to the other—the code for the second half of the third row of the composite can be copied from the code for the fifth row in the original, and other like relationships will soon be noticed. Put most simply, the codes for the first half of the composite PSIC 18 can be copied from the 20×20 codes, and one must only do the pasting as “left side-right side-left side,” . . . . Of course, that procedure will only work while still within the upper half of the composite PSIC 18, since the original PSIC 18 will not have included the code for the second half of the composite, and the identification of the binary code for the larger numbers will be required.

Now as to the XOR circuit itself, as is usually the case, a circuit the size of this XOR gate will be found to be made up of some combination of smaller gates, and such is the case here. The LNs 12 have been assigned letter designations for ease in identifying these sub-circuits, and turn out to be as follows (there are other combinations of such sub-circuits that will also yield an XOR gate): LNs 12 A and B form an OR gate; LNs 12 C and D form an AND gate; the E LN 12 forms a BYPASS gate; the F LN 12 forms a NOT gate; and the G and H LNs 12 form the output AND gate. This circuit demonstrates one vital role for the BYPASS gate in that the outputs of the OR gate and the NOT gate or inverter need to enter the output AND gate as the two inputs thereto, which is to say they must enter the G and H LNs 12 at the same time, but those OR gate and inverter outputs are not in the vertical alignment that such entry into the AND gate requires. The BYPASS gate (BYP) then acts to resolve that problem in geometry by placing the two LNs 12 of the output AND gate in vertical alignment.

The BYP is useful for a lot more than just make possible the completion of the structuring of some circuit, however. We take it that from all of the foregoing that the scalability of the ILA has been shown since, after all, nothing precludes the addition of yet one more PSIC 12 to whatever number may already be at hand. The execution of some operations such as addition leaves a number of scattered partial sums, and as shown in detail in the original application, the BYP can serve to bring those partial sums together, when joined with inverter pairs that will maintain the necessary voltage levels. What FIG. 15 also shows, however, is the coordinate feature of super-scalability, which is the second main objective of this IL Apparatus, and that emerges naturally from the feature of scalability.

As noted earlier, the “Computing Power” (CP) of an ILA is effectively measured by the size of the PSIC 18 in terms of the number of LNs 12. That is the case because it is only through inter-LN 12 connections that IP can be carried out, and an LN 12 has just two outward connections that can be employed. (Incoming connections are not counted because they already would already be counted as outgoing connections for the leftward and downward neighbor LNs 12, if any.) On the face of it, a 20×20 PSIC 18 would have 20×20×2=800 connections, but there are 20 LNs 12 along each of the side and top of the PSIC 18 that have no neighboring LN 12 to which connection could be made, thus to define a “Periphery Deficit” (PD) for this PSIC 18 of 2×20=40 connections. The resultant connection count is thus 800−40=760 connections, and the ratio of actual connections to that gross count is 760/800=0.95.

With both PS1 and PS2 at hand, with an X width of 40, the CP under the rule of scalability and a gross count would be 2(40×20)=1600. The PD for the PS1/PS2 of FIG. 15 is now 20+40=60, since the peripheries of the PS1/PS2 composite would now be 20 along the side and 40 across the top. The actual number of connections thus becomes 1600−60=1540, and the ratio is 1540/1600=0.9625. Twice the actual number of connections in PS1, or 2×760=1520, so with that 1540 connections in the PS1/PS2 composite PS 18 there are now more connections than what had previously been present beyond those derived from just doubling the original size and taking account of the PD. That gain comes from the fact that the PD of the composite PS 18 is relatively smaller (and the CP is correspondingly relatively larger), compared to the original PS1.

So looking at FIG. 15, the 40, 80, and the other LNs 12 in that rightward column of the PS1 PSIC 18 had not previously (in PS1 alone) had any LNS 12 to which there could be any rightward connection until that joinder between PS1 and PS2 had been made. Instead of having a CP of 1520 according to the rule of scalability, the new PS1/PS2 PSIC 18 has a CP of 2(40×20)−60=1600−60=1540, for a gain of 20 connections in accordance with a rule of super-scalability. That gain is seen to occur in the LNs 12 that lie along the right side of the original, single PS1 PSIC 18, i.e., in column 5, which had lacked any LNs 12 to which connection could be made before the joinder, but after the joinder have such LNs 12 available, since with the joinder there is now a column six. A PSIC 18 that has twice the number of LNs 12 of a reference PSIC 18 but more connections than just twice the number of those of the reference PSIC 18 exhibits super-scalability.

It is worth noting that the ability of the ILA to exhibit super-scalability is actually a matter of mathematic (geometric) certainty. The area of a square is d², where d is the length of a side, and the periphery of the square is 4d, with the periphery/area ratio being given by 4d/d²=4/d. With increasing d, and the periphery being increased linearly, the area will increase geometrically, i.e., as the square of length d. That exact relationship is of course changed with the calculation of a PD, but the underlying relationship will remain essentially the same: the effect of having a periphery (and hence fewer connections) will decrease in proportion to the size as the object (the PSIC 18) gets larger. Doubling the size of the object will give more connections than just twice the original, and a like calculation would be true of any other multiple.

With the joinder, the area of the composite PS1-PS2 PSIC 18 becomes d×2d=20×40=800, or 1600 prospective connections, and the “Peripheral Deficit” (or PD) become 3d=3(20)=60, so the number of actual connections becomes 1600−60=1540, and the ratio of the actual connections to the gross number is 1540/1600=0.9625, as compared to the ratio of 0.95 for the original PS1. It is like blowing up a balloon: the volume of a sphere increases faster than the circumference as the balloon is blown up. (With a PSIC 18 of 1,000 square, the PD would be 2,000 and the gross count would be 2(1,000×1,000)=2,000,000 to yield (2,000,000−2,000)/2,000,000=0.999.)

A measure of the effect of adding the second PSIC 18 to the first can be obtained from a comparison of the ratios of the evident number of connections before and after that addition as to the composite PS1-PS2 PSIC 18, which is 1540/1600=0.9625, and the same for PS1 alone, which is 760/800=0.95, and the ratio of those two is 0.9625/0.95=1.013. In other words, the PS1-PS2 PSIC 18 is 1.3, i.e., about one and a third percent more effective in providing actual connections than is the single PS1, which is the effect of super-scalability. The size of the increase in the connections count is thus relatively small, but even the slightest gain in the connections count suffices to constitute a degree of super-scalability.

The number of LNs 12 in the PS1/PS2 composite is exactly twice the number in the original PS1, so the only way in which the CP could have been increased beyond that doubling is if some LNs 12 in PS1 that could make no connections prior to the joinder of PS2, but had somehow gained the ability to do so when PS2 was added. Such is the case, and as has already been pointed out, the LNs 12 that have “magically” gained that connection power are those along the “Processing Space Cut Line” (PSCL) shown in FIG. 15 (Sheet 12), along which the joinder to PS2 is made. The very act of joining the two chips, in fact, takes place entirely in the formation of new connections through the SPTs 14 of what had been peripheral LNs 12 to the input lines of PS2. Together with the V_(dd) and GND lines, those SPTs 14 connect from the OLN output lines of PS1 (the “1” or “2” group of lines) to the RLN input lines of PS2 (the “3” or “4” group of lines) through the physical contact of the ends of the respective Signal Lines of PS1 and PS2, and similarly as to V_(dd) and GND. The effort to eliminate the von Neumann Bottleneck thus exhibited the feature of scalability, and the process of applying the power of scalability brought out the power of super-scalability as well, and caused the execution of super-scalability.

CONCLUSIONS

As can best be determined by this inventor, the concepts of IL stand poised to bring about a substantial change in the way in which the electronics industry, particularly as to computers, conducts its business. In using the methodology of IL, some real world problem would first have been identified and modeled by an algorithm, then expressed by an electronic circuit (in the present embodiment) made up of a series of properly interconnected binary logic gates. That circuit would then be encoded into a CODE block in memory that when applied would carry out those operations that were needed to execute that algorithm. Each operation would rest on a continuous flow of enabling bits into the PTs, together with a like flow of data bits, either internally or by way of a number of I/Os 16, whether from memory or at some points from a foreign source as to any part of an algorithm that required external data input, from which input a constant flow of output data based on the algorithm and any such input data would emerge. After the first input stage of the algorithm, each step will operate on the data created by the preceding circuits and any added data.

In current practice, an effort has been made in the industry to be “all things to all people,” i.e., to provide in one apparatus what was almost a turnkey machine for a wide range of different end user types, those end users having been provided with any number of complex (yet not particularly effective) programs that take up a lot of space and will often never be used but still had to be paid for. There has thus grown up a “cottage industry”—actually a variety of different cottage industries specializing in different computer operations—of software-based companies that specialize in particular tasks, such as CAD, data bases, word processing, multimedia, and so on, but would soon end up seeing the end user scanning the internet, the Yellow Pages, or the local software outlets looking for that one truly effective program that the end user wishes had been in his computer in the first place.

Instead, one can envision a marketplace in which computers come in a CAD model, a data base model, a word processing model, etc., in which each model comes with a “top of the line” version of a program that treats the particular task at the highest level possible. These different types could also be directed towards particular professions, such as an attorney version, an EE version, a physicist version, etc. There would of course be substantial overlap, but the end user would be invited to select the particular features desired, with some differences between, say, a chemical engineer and a mechanical engineer, particularly in the kind of supporting data bases and mathematical programs that would be included in the different engineering packages.

However, back to IL, one can instead envisage that, first impressions perhaps to the contrary, it would certainly fall within the purview of any competent electronics engineer to absorb the essentials of the IL procedures, and to develop code lines for any algorithm that could be written for some particular task. For that reason, one can also envision an IL product made up of a number of PSIC modules of a convenient size, a Control Cable and wiring harness (see parent application), a Logic Node Locator, and the requisite number of Circuit Code Selectors and Signal Code Selectors for each module, and a tower or laptop with mother board to include all of the above in plug-in form. The end user would construct his own IL computer, or negotiate with a local dealer to have that done, and a computer tailored to the task, unfettered by the presence of myriad programs having no use to the present user but act only to slow down the desired work, would result.

As to what model this IL version would constitute, the answer is: “All of the above.” The end user would know his or her own specialty, what the problems were, what kinds of algorithms could be written and what were the circuits that would be needed to execute those algorithms, what binary logic gate circuits would be needed, etc., etc. Each end user would design his or her own special model of an IL system.

That investment is justified by what has been said herein. If by “speed” one means the throughput, the unlimited scalability of IL leaves a freedom to incorporate in an ILA as many modules of Processing Space as may be required to achieve any given throughput. But as to “speed” in the strict sense (i.e., FPS), with the von Neumann Bottleneck having been removed the successive steps of the algorithm will follow each other without interruptions, cycle by cycle, so except for cases of data dependence there will be no “wait states” during which no IP would be taking place. But absent an unlikely event of any data dependence (the timing of the encoding of the PTs would generally forestall any data dependence), the basic operating speed of IL should be significantly faster than anything now achieved using microprocessor-based apparatus with their inherent inclusion of the von Neumann Bottleneck. In terms of the underlying methodology, this would seem to be the fastest way possible for IP to be carried out, although technologies other than semiconductor electronics will likely end up making the process even faster. As a consequence relative to the commercial and industrial applicability of IL, it would seem that there is little if any doubt that this procedure provides a pathway to a scalable and super-scalable supercomputer that would have as much speed and data-handling capability as might be desired, without limit.

As one particular example in the Artificial Intelligence field, the brain is thought to be an array of multiply interconnected synapses, and the PS of IL (in the example used herein) is an array of multiply interconnected transistors. The IL connections shown herein do not, of course, represent any limit to the kinds of interconnections that could be made, so it seems nothing would prevent there being developed a more complete model of the brain. In terms of natural arrays, such as the various crystal classes, the model used herein is based on the simple cubic structure. Should the problem of off-chip connection to the on-chip PTs that serve to structure the required circuitry be better solved, much more sophisticated designs might well be considered. For example, while this IL model is only a 2-D embodiment taken from the simple cubic crystal class, other crystal structures present 8 or 12 facets, and at least using discrete transistors those geometric structures could be modeled just as well, perhaps thereby to yield better models of the brain.

Whatever may be the validity of the foregoing projections, however, it can be reasonably asserted that the potential scope of IL use extends throughout the full range of current microprocessor or FPGA, etc., usage, and in terms of speed (throughput), volume (how much data could be handled), and precision (how many bits could there be in a number expression) would likely surpass anything that those current devices could accomplish.

IL seems to provide the “breakthrough”—as the “revolutionary” rather than the “evolutionary” advance—that Tosic had sought, and would justify at least the kind of investment that went into the ENIAC. (The ENIAC investment can be seen in the size of the apparatus, that had occupied 1800 ft² and consumed 174 kW of power, at an approximate cost of the basic system of $750,000 plus approximately $30,000 for magnetic storage, all in 1940's dollars.) Nancy Stern, From ENIAC to UNIVAC: An Appraisal of the Eckert-Mauchly Computers (Digital Press, Digital Equipment Corporation, Bedford, Mass., 1981), p. 51. Another sense of the size of the ENIAC can be extracted from the photographs of the machine on pages 31, 35, 40, and 43, and then a weight of over 30 tons, p. 73. Of course, much of that size comes from using vacuum tube circuitry, but that is still a huge and costly apparatus. An investment of that size compared to the gain achieved suggests that a sufficient investment in IL to produce a fully operational apparatus would also be well justified, looking at the same kinds of parameters. The evolution of the ENIAC to the UNIVAC and onward would no doubt be carried out again, by a like evolution by resolving some of the fairly obvious problems in this current IL model, from this basic IL Apparatus to the more sophisticated apparatus noted above, or such like or even better apparatus.

In short, the principle conclusions derived from the appearance of IL is that the electronics industry can now see new life, with the appearance of new kinds of faster and all-around better products, more easily tailored to the needs of a wide range of new markets, such as to provide a near explosion in new employment opportunities and particularly new intellectual challenges that have not yet been seen. The development, construction, and of beta testing of an IL prototype now stands as a critical step in the future utilization of that technology.

What stands in the way of such an expansion, besides the “NIH” (Not Invented Here) syndrome, is the industry mind set, and the kind of complacency that locks out any real progress. This inventor was told by an upper level manager in one top level company that “we have millions of lines of code written here, and that code will continue to be in use long after you and I are long gone.” It amounts to protecting the investment, even as the return on that investment continues to shrink, and even as the possibility of continued growth is being blocked by the laws of physics that pertain to integrated circuit design, so that all that can be done within the current paradigm, as suggested by Tosic, is to nibble away at the edges.

COMPONENT PLACEMENTS, NUMBERING AND ABBREVIATIONS

-   CPT1: DRR to V_(dd) -   CPT2: GA to I/O -   CPT3: SO to GND -   10 Processing Space (PS) -   12 Logic Node (LN) -   14 Signal Pass Transistor (SPT) -   16 I/O -   18 PS Integrated Circuit (PSIC) -   20 Drain Terminal (DR) -   22 Gate Terminal (GA) -   24 Source Terminal (SO) -   26 Pedestal (PED) -   28 Drain Signal Line (DTL) -   30 Gate Signal Line (GTL) -   32 Source Signal Line -   34 IN_(j) Locator -   36 LI_(i) Entry -   38 +/−₁ Entry -   40 XNOR -   42 Reference Register₁ (RR₁) -   44 r₁ Entry -   46 +/−₂ Entry -   48 XNOR -   50 RR2 -   52 k_(i) Entry -   54 X_(M) Entry -   56 IN_(j) Output -   58 Top Entry Aperture -   60 Contact Pin (CP) -   62 Contact Aperture -   64 Bit Entry Rod (BER) 

1. A scalable and super-scalable information processing apparatus, comprising: At least a first processing space comprising an array of independently controllable energy transmitting information processing elements that encompass a first area having a first periphery, said information processing elements having access to power means and data input means, with said first area encompassing a planar surface of said at least a first processing space, said at least a first processing space having a pre-determined dimensionality and pressure contact means on each of a number of sides thereof that comport with said dimensionality and are disposed normally to said planar surface, with said information processing elements being disposed in rows and columns within said first area, said disposition of said information processing elements placing said information processing elements in repetitive side-by-side relationships in each said dimension; Control means by which code may be entered into said processing spaces to bring about connections between said energy transmitting information processing elements and from said energy transmitting information processing elements to said power means and said data input means; Wherein, by the entry of code through said control means, information processing can be rendered possible by accessing said power means and said data input means, and selectively interconnecting said energy transmitting information processing elements in such a number of directions as is defined by said dimensionality of said at least a first processing space; Wherein having one said energy transmitting information processing element in a side-by-side relationship with another said energy transmitting information processing element forms a connection possibility, said connection possibilities being limited in number only by the number of said energy transmitting information processing elements being present; with The number of separate connection possibilities present within said at least a first processing space establishing the computing power of said information processing apparatus; wherein Upon making connection from said power means to said at least a first said energy transmitting information processing element and from said at least a first said energy transmitting information processing element to another said energy transmitting information processing element constitutes an information processing possibility; Upon creating at least one said information processing possibility and entering a signal into said information processing possibility through said data input means or from a preceding information processing element, with said signal then passing on from said information processing possibility to at least one more of said energy transmitting information processing elements and eliciting a response from said at least one more energy transmitting information processing element constitutes an information processing event; Whereby, through addition to said at least one said information processing element of an arbitrary number of more said information processing elements, said computing power of said at least a first processing space will increase accordingly, Thus to exhibit scalability.
 2. The information processing apparatus of claim 1; wherein Said energy transmitting information processing elements that lie within a row or column bordering said periphery have at least one direction in which no energy transmitting information processing element to which connection could be made is present, and is thus not able to provide a connection opportunity; However, adding to said first processing space at least one more said processing space of like structure as said first processing space by interconnection of at least one said energy transmitting information processing element that lies within said periphery of said first processing space to a like said energy transmitting information processing element that is disposed within a periphery of said at least one more processing space will produce a composite processing space having a new area and a new periphery; and Upon connecting said at least one more said processing space to said at least a first processing space through said energy transmitting information processing elements that lie within a row or column bordering said periphery and said pressure contact means to form said composite processing space, the number of connection opportunities present in said composite processing space will be greater than the sum of the connection opportunities in said at least a first processing space and said at least one more processing space, and consequently, The computing power of said composite processing space will be greater than the sum of the computing powers of said at least a first processing space and said at least one more processing space, thus to exhibit super-scalability.
 3. Apparatus for information processing, comprising: An array of passive energy transmitting devices, each having a number of connectible terminals thereon disposed along directions as defined by the dimensionality of said array, each of said passive energy transmitting devices being capable of being transformed into a corresponding active energy transmitting device capable of receiving energy packets having information contained therein and performing information processing on said energy packets; An array of active energy transmitting devices having proximal and distal ends, said active energy transmitting devices being capable of passing through energy packets upon the imposition thereto of an enabling signal, with said proximal ends of said active energy transmitting devices being connected respectively to different ones of said connectible terminals on said passive energy transmitting devices, and said distal ends of said active energy transmitting devices being connected respectively to: An energy source, an entry location for energy packets, an energy sink, and said number of connectible terminals are disposed on at least one other of said passive energy transmitting devices; and Addressing means by which enabling signals can be directed to selected ones of said active energy transmitting devices; whereupon The imposition of an enabling signal onto one or more of said active energy transmitting devices connected to one or more of said passive energy transmitting devices that await the entry therein of said energy packets will transform said one or more passive energy transmitting devices into corresponding active energy transmitting devices that will perform information processing upon the entry of energy packets into said entry location for energy packets.
 4. The information processing apparatus of claim 2 wherein: Said energy comprises electronic energy; Said energy transmitting information processing elements comprise operational transistors having a number of terminals connected thereto; An array of pass transistors that connect respectively between said terminals of said operational transistors and said terminals of at least one other said operational transistor, said power means, and said data input means; Said power means comprises connection to V_(dd) on one side of said operational transistor and to GND on an opposite side of said operational transistor; An array of code selectors respectively connected to said pass transistors that are connected to said operational transistor; whereby An enabling of selected ones of said pass transistors would cause the structuring of an operable binary logic circuit; An entry of a data bit into said operational transistors would bring about an information processing event, whereby The full processing of said data would bring about the execution of an algorithm that expressed a particular arithmetical/logical problem.
 5. The information processing apparatus of claim 4 further comprising: An integrated circuit having terminal lines connected to said operational transistors including circuit lines that connect to said power means and to an input/output terminal and signal lines that connect through pass transistors to terminals of said another said operational transistor; Said pressure contact means comprises extensions of said Vdd, GND, and signal lines beyond the periphery of the integrated circuit sufficiently to permit a firm electrical contact to be made between said extensions of a first said integrated circuit and of at least one more integrated circuit; Said signal lines render possible the joinder of one said processing space to another said processing space in electrical continuity; thereby To permit the occurrence of information processing events through the joinder of one said at least a first processing space to said at least one more processing space; thereby: To permit the structuring of binary logic circuits both within both said at least a first processing space and said at least one more processing space and within the joinder of said at least a first processing space and said at least one more processing space; thus To permit the structuring of a composite processing space of unlimited size, speed, and data handling capacity, and thereby to exhibit super-scalability.
 6. The information processing apparatus of claim 5 wherein Said information processing apparatus is fabricated on an integrated circuit chip having four edges; and Each said edge comprises a cut line along which are disposed a row or column of operational transistors designated as peripheral transistors, with pass transistors connected thereto and to said terminals of said at least one more processing space, wherein An enabling of said pass transistors serves both to permit the joinder of one said at least a first processing space and said at least one more processing space, and the structuring of a binary logic circuit that permits the occurrence of an information processing event; thereby To permit the structuring of binary logic circuits both within said processing space and through the joinder of said at least a first processing space and said at least one more processing space; thus To permit the structuring of a composite processing space of unlimited size, speed, and data handling capacity.
 7. The super-scalable information processing apparatus of claim 6 wherein said energy is electronic energy, said passive energy transmitting information processing elements are operational transistors, and said active energy transmitting information processing elements are pass transistors.
 8. The super-scalable information processing apparatus of claim 7 wherein, by the enabling of selected ones of said connections, binary logic circuits can be structured that are capable of receiving operational data and processing said data such that an algorithm that expresses a particular arithmetic/logical problem can be executed.
 9. The super-scalable information processing apparatus of claim 8 wherein processing spaces are formed on separate integrated circuits, and said integrated circuits each comprise a first array of passive transistors and a second array of active transistors connected at proximal ends thereof to respective passive transistors, wherein respective ones of said array of active transistors also connect at distal ends thereof to an energy source, a source of external data input, and an energy sink, respectively, thus to convert said passive transistors into active transistors, and respective ones of said active transistors of said second array serve to make connection between said terminals of at least one said active transistor of at least one processing space and said terminals of another active transistor of at least one more processing space.
 10. The super-scalable information processing apparatus of claim 1 further comprising; Code controlled switching means within said connections between said one or more of said terminals of one said processing element to one or more said terminals of an adjacent said processing element, whereby; By opening or closing said connections so as to structure said one or more processing elements into a desired circuit or part thereof; and Providing code to said switching means that will bring about such opening or closing thereof, thus to structure desired circuits that are applicable to the execution of one or more algorithms; and Employing data entrance means to enter such data as may be necessary to execute said algorithms, Thus to carry out information processing. 